Eletrônica - Analysis and Design of Analog Integrated Circuits with solutions - (Gray-Meyer), Manuais, Projetos, Pesquisas de Engenharia Elétrica

Baixe Eletrônica - Analysis and Design of Analog Integrated Circuits with solutions - (Gray-Meyer) e outras Manuais, Projetos, Pesquisas em PDF para Engenharia Elétrica, somente na Docsity! Fourth Edition GRAY HURST LEWIS MEYER ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWlS University of California, Davis ROBERT G. MEYER University of California, Berkeley JOHN WlLEY & SONS, INC. New York / Chichester / Weinheim /Brisbane /Singapore / Toronto viii Preface as in the teaching of courses on this subject, and this experience is reflected in the choice of text material and in the problem sets. Although this book is concerned largely with the analysis and design of ICs, a consid- erable amount of material is also included on applications. In practice, these two subjects are closely linked, and a knowledge of both is essential for designers and users of ICs. The latter compose the larger group by far, and we believe that a working knowledge of IC design is a great advantage to an IC user. This is particularly apparent when the user mdst choose from among a number of competing designs to satisfy a particular need. An understanding of the IC structure is then useful in evaluating the relative desirability of the different designs under extremes of environment or in the presence of variations in supply voltage. In addition, the IC user is in a much better position to interpret a manufacturer's data if he or she has a working knowledge of the internal operation of the integrated circuit. The contents of this book stem largely from courses on analog integrated circuits given at the University of California at the Berkeley and Davis campuses. The courses are un- dergraduate electives and first-year graduate courses. The book is structured so that it can be used as the basic text for a sequence of such courses. The more advanced mate- rial is found at the end of each chapter or in an appendix so that a first course in analog integrated circuits can omit this material without loss of continuity. An outline of each chapter is given below together with suggestions for material to be covered in such a first course. It is assumed that the course consists of three hours of lecture per week over a 15-week semester and that the students have a working knowledge of Laplace transforms and frequency-domain circuit analysis. It is also assumed that the students have had an introductory course in electronics so that they are familiar with the principles of transistor operation and with the functioning of simple analog circuits. Unless otherwise stated, each chapter requires three to four lecture hours to cover. Chapter 1 contains a summary of bipolar transistor and MOS transistor device physics. We suggest spending one week on selected topics from this chapter, the choice of topics depending on the background of the students. The material of Chapters 1 and 2 is quite important in IC design because there is significant interaction between circuit and device design, as will be seen in later chapters. A thorough understanding of the influence of device fabrication on device characteristics is essential. Chapter 2 is concerned with the technology of IC fabrication and is largely descriptive. One lecture on this material should suffice if the students are assigned to read the chapter. Chapter 3 deals with the characteristics of elementary transistor connections. The ma- terial on one-transistor amplifiers should be a review for students at the senior and gradu- ate levels and can be assigned as reading. The section on two-transistor amplifiers can be covered in about three hours, with greatest emphasis on differential pairs. The material on device mismatch effects in differential amplifiers can be covered to the extent that time allows. In Chapter 4, the important topics of current mirrors and active loads are considered. These configurations are basic building blocks in modern analog IC design, and this ma- terial should be covered in full, with the exception of the material on band-gap references and the material in the appendices. Chapter 5 is concerned with output stages and methods of delivering output power to a load. Integrated-circuit realizations of Class A, Class B, and Class AB output stages are described, as well as methods of output-stage protection. A selection of topics from this chapter should be covered. Chapter 6 deals with the design of operational amplifiers (op amps). Illustrative exam- ples of dc and ac analysis in both MOS and bipolar op amps are performed in detail, and the limitations of the basic op amps are described. The design of op amps with improved Preface ix characteristics in both MOS and bipolar technologies is considered. This key chapter on amplifier design requires at least six hours. In Chapter 7, the frequency response of amplifiers is considered. The zero-value time- constant technique is introduced for the calculations of the -3-dB frequency of complex circuits. The material of this chapter should be considered in full. Chapter 8 describes the analysis of feedback circuits. Two different types of analysis are presented: two-port and return-ratio analyses. Either approach should be covered in full with the section on voltage regulators assigned as reading. Chapter 9 deals with the frequency response and stability of feedback circuits and should be covered up to the section on root locus. Time may not pennit a detailed discussion of root locus, but some introduction to this topic can be given. In a 15-week semester, coverage of the above material leaves about two weeks for Chapters 10, 11, and 12. A selection of topics from these chapters can be chosen as follows. Chapter 10 deals with nonlinear analog circuits, and portions of this chapter up to Section 10.3 could be covered in a first course. Chapter 11 is a comprehensive treatment of noise in integrated circuits, and material up to and including Section 11.4 is suitable. Chapter 12 describes fully differential operational amplifiers and common-mode feedback and may be best suited for a second course. We are grateful to the following colleagues for their suggestions for andor eval- uation of this edition: R. Jacob Baker, Bemhard E. Boser, A. Paul Brokaw, John N. Churchill, David W. Cline, Ozan E. Erdogan, John W. Fattaruso, Weinan Gao, Edwin W. Greeneich, Alex Gros-Balthazard, Tiinde Gyurics, Ward J. Helms, Timothy H. Hu, Shafiq M. Jamal, John P. Keane, Haideh Khorramabadi, Pak-Kim Lau, Thomas W. Matthews, Krishnaswamy Nagaraj, Khalil Najafi, Borivoje NikoliC, Robert A. Pease, Lawrence T. Pileggi, Edgar Shnchez-Sinencio, Bang-Sup Song, Richard R. Spencer, Eric J. Swanson, Andrew Y. J. Szeto, Yannis P. Tsividis, Srikanth Vaidianathan, T. R. Viswanathan, Chomg- Kuang Wang, and Dong Wang. We are also grateful to Kenneth C. Dyer for allowing us to use on the cover of this book a die photograph of an integrated circuit he designed and to Zoe Marlowe for her assistance with word processing. Finally, we would like to thank the people at Wiley and Publication Services for their efforts in producing this fourth edition. The material in this book has been greatly influenced by our association with Donald 0. Pederson, and we acknowledge his contributions. Berkeley and Davis, CA, 2001 Paul R. Gray Paul J. Hurst Stephen H. Lewis Robert G. Meyer Contents . CHAPTER l Models for Integrated-Circuit Active Devices 1 Introduction 1 Depletion Region of a pn Junction 1 1.2.1 Depletion-Region Capacitance 5 1.2.2 JunctionBreakdown 6 Large-Signal Behavior of Bipolar Transistors 8 1.3.1 Large-Signal Models in the Forward-Active Region 9 1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region 14 1.3.3 Saturation and Inverse Active Regions 16 1.3.4 Transistor Breakdown Voltages 20 1.3.5 Dependence of Transistor Current Gain PF on Operating Conditions 23 Small-Signal Models of Bipolar Transistors 26 1.4.1 Transconductance 27 1.4.2 Base-Charging Capacitance 28 1.4.3 Input Resistance 29 1.4.4 Output Resistance 29 1.4.5 Basic Small-Signal Model of the Bipolar Transistor 30 1.4.6 Collector-Base Resistance 30 1.4.7 Parasitic Elements in the Small-Signal Model 3 1 1 A.8 Specification of Transistor Frequency Response 34 Large Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 38 1.5.1 Transfer Characteristics of MOS 1 S.2 Comparison of Operating Regions of Bipolar and MOS Transistors 45 1 S.3 Decomposition of Gate-Source Voltage 47 1.5.4 Threshold Temperature Dependence 47 1.5.5 MOS Device Voltage Limitations 48 1.6 Small-Signal Models of the MOS \/Transistors 49 1.6.1 Transconductance 50 1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance 51 1.6.3 InputResistance 52 1.6.4 Output Resistance 52 1.6.5 Basic Small-Signal Model of the MOS Transistor 52 1.6.6 Body Transconductance 53 1.6.7 Parasitic Elements in the Small-Signal Model 54 1.6.8 MOS Transistor Frequency Response 55 1.7 Short-Channel Effects in MOS Transistors 58 1.7.1 Velocity Saturation from the Horizontal Field 59 1.7.2 Transconductance and Transition Frequency 63 1.7.3 Mobility Degradation from the Vertical Field 65 1.8 Weak Inversion in MOS Transistors 65 1 .S. 1 Drain Current in Weak Inversion 66 1.8.2 Transconductance and Transition Frequency in Weak Inversion 68 1.9 Substrate Current Flow in MOS Transistors 7 1 A. 1.1 Summary of Active-Device Devices 38 Contents xiii 4.3.4 Common-Emitter/Common-Source Amplifier with Diode-Connected Load 284 4.3.5 Differential Pair with Current-Mirror Load 287 4.3.5.1 Large-Signal Analysis 287 4.3.5.2 Small-Signal Analysis 288 4.3.5.3 Common-Mode Rejection Ratio 293 4.4 Voltage and Current References 299 4.4.1 Low-Current Biasing 299 4.4.1.1 Bipolar Widlar Current Source 299 4.4.1.2 MOS Widlar Current Source 302 4.4.1.3 Bipolar Peaking Current Source 303 4.4.1.4 MOS Peaking Current Source 304 4.4.2 Supply-Insensitive Biasing 306 4.4.2.1 Widlar Current Sources 306 4.4.2.2 Current Sources Using Other Voltage Standards 307 4.4.2.3 Self Biasing 309 4.4.3 Temperature-Insensitive Biasing 317 4.4.3.1 Band-Gap-Referenced Bias Circuits in Bipolar Technology 3 17 4.4.3.2 Band-Gap-Referenced Bias Circuits in CMOS Technology 323 A.4.1 Matching Considerations in Current Mirrors 327 A.4.1.1 Bipolar 327 A.4.1.2 MOS 329 A.4.2 Input Offset Voltage of Differential Pair with Active Load 332 A.4.2.1 Bipolar 332 A.4.2.2 MOS 334 CHAPTER 5 Output Stages 344 5.1 Introduction 344 5.2 The Emitter Follower As an Output Stage 344 5.2.1 Transfer Characteristics of the Emitter-Follower 344 5.2.2 Power Output and Efficiency 347 5.2.3 Emitter-Follower Drive Requirements 354 5.2.4 Small-Signal Properties of the Emitter Follower 355 5.3 The Source Follower As an Output Stage 356 5.3.1 Transfer Characteristics of the Source Follower 356 5.3.2 Distortion in the Source Follower 358 5.4 Class B Push-Pull Output Stage 362 5.4.1 Transfer Characteristic of the Class B Stage 363 5.4.2 Power Output and Efficiency of the Class B Stage 365 5.4.3 Practical Realizations of Class B Complementary Output Stages 369 5.4.4 All-npn Class B Output Stage 376 5.4.5 Quasi-Complementary Output Stages 379 5 A.6 Overload Protection 3 80 5.5 CMOS Class AB Output Stages 382 5 S. 1 Common-Drain Configuration 3 83 5 S.2 Common-Source Configuration with Error Amplifiers 384 5.5.3 Alternative Configurations 391 5.5.3.1 Combined Common-Drain Common-Source Configuration 39 1 5.5.3.2 Combined Common-Drain Common-Source Configuration with High Swing 393 5 S.3.3 Parallel Common-Source Configuration 394 CHAPTER 6 Operational Amplifiers with Single-Ended Outputs 404 6.1 Applications of Operational Amplifiers 405 xiv Contents 6.1.1 Basic Feedback Concepts 405 6.1.2 Inverting Amplifier 406 6.1.3 Noninverting Amplifier 408 6.1.4 Differential Amplifier 408 6.1.5 Nonlinear Analog Operations 409 6.1.6 Integrator, Differentiator 4 10 6.1.7 Internal Amplifiers 41 1 6.1.7.1 Switched-Capacitor Amplifier 411 6.1.7.2 Switched-Capacitor Integrator 416 6.2 Deviations from Ideality in Real Oper- ational Amplifiers 419 6.2.1 Input Bias Current 419 6.2.2 Input Offset Current 420 6.2.3 Input Offset Voltage 421 / -,/6.2.4 Common-Mode Input Range 421 $.2.5 Common-Mode Rejection Ratio / / (CMRR) 421 $2.6 Power-Supply Rejection Ratio I ' L/ (PSRR) 422 6.2.7 Input Resistance 424 6.2.8 Output Resistance 424 6.2.9 Frequency Response 424 6.2.10 Operational-Amplifier Equivalent Circuit 424 Basic Two-Stage MOS Operational Amplifiers 425 6.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain 426 6.3.2 Output Swing 428 6.3.3 Input Offset Voltage 428 6.3.4 Common-Mode Rejection Ratio 1 431 6.3.5 Common-Mode Input Range 432 6.3.6 Power-Supply Rejection Ratio (PSRR) 434 6.3.7 Effect of Overdrive Voltages 439 6.3.8 Layout Considerations 439 Two-Stage MOS Operational Amplifiers with Cascodes 442 MOS Telescopic-Cascode Operational Amplifiers 444 6.6 MOS Folded-Cascode Operational Amplifiers 446 6.7 MOS Active-Cascode Operational Amplifiers 450 6.8 Bipolar Operational Amplifiers 453 6.8.1 The dc Analysis of the 741 Operational Amplifier 456 6.8.2 Small-Signal Analysis of the 741 Operational Amplifier 461 6.8.3 Input Offset Voltage, Input Offset Current, and Cornmon-Mode Rejection Ratio of the 741 470 6.9 Design Considerations for Bipolar Monolithic Operational Amplifiers 472 6.9.1 Design of Low-Drift Operational Amplifiers 474 6.9.2 Design of Low-Input-Current Operational Amplifiers 476 CHAPTER 7 Frequency Response of Integrated Circuits 488 7.1 Introduction 488 7.2 Single-Stage Amplifiers 488 7.2.1 Single-Stage Voltage Amplifiers and The Miller Effect 488 7.2.1.1 The Bipolar Differential Amplifier: Differential- Mode Gain 493 7.2.1.2 The MOS Differential Amplifier: Differential- Mode Gain 496 7.2.2 Frequency Response of the Cornrnon-Mode Gain for a Differential Amplifier 499 7.2.3 Frequency Response of Voltage Buffers 502 7.2.3.1 Frequency Response of the Emitter Follower 503 7.2.3.2 Frequency Response of the Source Follower 509 7.2.4 Frequency Response of Current Buffers 511 7.2.4.1 Common-Base-Amplifier Frequency Response 5 14 7.2.4.2 Common-Gate-Amplifier Frequency Response 5 15 Contents xv 7.3 Multistage Amplifier Frequency Response 516 Dominant-Pole Approximation 5 l 6 Zero-Value Time Constant Analysis 517 Cascode Voltage-Amplifier Frequency Response 522 Cascode Frequency Response 5 25 Frequency Response of a Current Mirror Loading a Differential Pair 532 Short-circuit Time Constants 533 7.4 Analysis of the Frequency Response of the 741 Op Amp 537 7.4.1 High-Frequency Equivalent Circuit of the741 537 7.4.2 Calculation of the -3-dB Frequency of the 741 538 7.4.3 Nondominant Poles of the 741 540 7.5 Relation Between Frequency Response and Time Response 542 CHAPTER 8 Feedback 553 Ideal Feedback Equation 553 Gain Sensitivity 555 Effect of Negative Feedback on Distortion 555 Feedback Configurations 557 8.4.1 Series-Shunt Feedback 8.4.2 Shunt-Shunt Feedback 8.4.3 Shunt-Series Feedback 8.4.4 Series-Series Feedback Practical Configurations and of Loading 563 8.5.1 Shunt-Shunt Feedback 8.5.2 Series-Series Feedback 8.5.3 Series-Shunt Feedback 8.5.4 Shunt-Series Feedback 8.5.5 Summary 587 Single-Stage Feedback 587 8.6.1 Local Series Feedback 557 560 561 562 the Effect 563 569 579 583 5 87 8.6.2 Local Shunt Feedback 591 The Voltage Regulator as a Feedback Circuit 593 Feedback Circuit Analysis Using Return Ratio 599 8.8.1 Closed-Loop Gain Using Return Ratio 601 8.8.2 Closed-Loop Impedance Formula Using Return Ratio 607 8.8.3 Summary-Return-Ratio Analysis 612 Modeling Input and Output Ports in Feedback Circuits 6 13 CHAPTER 9 Frequency Response and Stability of Feedback Amplifiers 624 Introduction 624 Relation Between Gain and Bandwidth in Feedback Amplifiers 624 Instability and the Nyquist Criterion 626 Compensation 633 9.4.1 Theory of Compensation 633 9.4.2 Methods of Compensation 637 9.4.3 Two-Stage MOS Amplifier Compensation 644 9.4.4 Compensation of Single-Stage CMOS OP Amps 652 9.4.5 Nested Miller Compensation 656 Root-Locus Techniques 664 9.5.1 Root Locus for a Three-Pole Transfer Function 664 9.5.2 Rules for Root-Locus Construction 667 9.5.3 Root Locus for Dominant-Pole Compensation 675 9.5.4 Root Locus for Feedback-Zero Compensation 676 Slew Rate 680 9.6.1 Origin of Slew-Rate Limitations 680 9.6.2 Methods of Improving Slew-Rate 684 xviii Symbol Convention Symbol Convention Unless otherwise stated, the following symbol convention is used in this book. Bias or dc quantities, such as transistor collector current Ic and collector-emitter voltage VCE, are represented by uppercase symbols with uppercase subscripts. Small-signal quantities, such as the incremental change in transistor collector current i,, are represented by lowercase symbols with lowercase subscripts. Elements such as transconductance g, in small-signal equivalent circuits are represented in the same way. Finally, quantities such as total collector current I,, which represent the sum of the bias quantity and the signal quantity, are represented by an uppercase symbol with a lowercase subscript. Modeisfor Integrated-Circuit Active Devices 1.1 Introduction The analysis and design of integrated circuits depend heavily on the utilization of suitable models for integrated-circuit components. This is true in hand analysis, where fairly simple models are generally used, and in computer analysis, where more complex models are encountered. Since any analysis is only as accurate as the model used, it is essential that the circuit designer have a thorough understanding of the origin of the models commonly utilized and the degree of approximation involved in each. This chapter deals with the derivation of large-signal and small-signal models for integrated-circuit devices. The treatment begins with a consideration of the properties of pn junctions, which are basic parts of most integrated-circuit elements. Since this book is primarily concerned with circuit analysis and design, no attempt has been made to produce a comprehensive treatment of semiconductor physics. The emphasis is on summarizing the basic aspects of semiconductor-device behavior and indicating how these can be modeled by equivalent circuits. 1.2 Depletion Region of a pn Junction The properties of reverse-biased pn junctions have an important influence on the charac- teristics of many integrated-circuit components. For example, reverse-biased pn junctions exist between many integrated-circuit elements and the underlying substrate, and these junctions all contribute voltage-dependent parasitic capacitances. In addition, a number of important characteristics of active devices, such as breakdown voltage and output re- sistance, depend directly on the properties of the depletion region of a reverse-biased pn junction. Finally, the basic operation of the junction field-effect transistor is controlled by the width of the depletion region of a p n junction. Because of its importance and applica- tion to many different problems, an analysis of the depletion region of a reverse-biased pn junction is considered below. The properties of forward-biased pn junctions are treated in Section 1.3 when bipolar-transistor operation is described. Consider a pn junction under reverse bias as shown in Fig. 1.1. Assume constant doping densities of ND atoms/cm3 in the n-type material and NA atoms/cm3 in the p- type material. (The characteristics of junctions with nonconstant doping densities will be described later.) Due to the difference in carrier concentrations in the p-type and n-type regions, there exists a region at the junction where the mobile holes and electrons have been removed, leaving the fixed acceptor and donor ions. Each acceptor atom carries a negative charge and each donor atom carries a positive charge, so that the region near the junction is one of significant space charge and resulting high electric field. This is called 2 Chapter 1 Models for Integrated-Circuit Active Devices + +' VR (,) Applied external Charge density p t reverse bias --------- Distance -------------- I Electric jeld f l l 8 ! I ! I Potential 4 I Figure l . l The abrupt junc- tion under reverse bias VR. (a) Schematic. (b) Charge density. (C) Electric field. (d) Electro- static potential. the depletion region or space-charge region. It is assumed that the edges of the depletion region are sharply defined as shown in Fig. 1.1, and this is a good approximation in most cases. For zero applied bias, there exists a voltage $0 across the junction called the built-in potential. This potential opposes the diffusion of mobile holes and electrons across the junction in equilibrium and has a value1 where kT VT = - -- 26 mV at 300•‹K 4 the quantity ni is the intrinsic carrier concentration in a pure sample of the semiconductor and ni = 1.5 X 1010cm-3 at 300•‹K for silicon. In Fig. 1.1 the built-in potential is augmented by the applied reverse bias, VR, and the total voltage across the junction is ($0 + VR). If the depletion region penetrates a distance W , into the p-type region and Wz into the n-type region, then we require because the total charge per unit area on either side of the junction must be equal in mag- nitude but opposite in sign. 1.2 Depletion Region of a pn Junction 5 1.2.1 Depletion-Region Capacitance Since there is a voltage-dependent charge Q associated with the depletion region, we can calculate a small-signal capacitance C, as follows: Now where A is the cross-sectional area of the junction. Differentiation of (1.14) gives Use of (1.17) and ( l . 18) in (1.16) gives The above equation was derived for the case of reverse bias VR applied to the diode. However, it is valid for positive bias voltages as long as the forward current flow is small. Thus, if VD represents the bias on the junction (positive for forward bias, negative for reverse bias), then (1.19) can be written as where Cjo is the value of C j for VD = 0. Equations 1.20 and 1.21 were derived using the assumption of constant doping in the p-type and n-type regions. However, many practical diffused junctions more closely approach a graded doping profile as shown in Fig. 1.2. In this case a similar calculation yields Note that both (1.21) and (1.22) predict values of Cj approaching infinity as VD ap- proaches $0. However, the current flow in the diode is then appreciable and the equations no longer valid. A more exact analysis2v3 of the behavior of Cj as a function of VD gives the result shown in Fig. 1.3. For forward bias voltages up to about $012, the values of Cj predicted by (1.21) are very close to the more accurate value. As an approximation, some computer programs approximate Cj for VD > $012 by a linear extrapolation of (1.21) or (1.22). 1 6 Chapter 1 Models for Integrated-Circuit Active Devices Charge density p Figure 1.2 Charge density versus dis- tance in a graded junction. --. More accurate calculation Reverse bias 1 Foward bias Figure 1.3 Behavior of pn junction depletion-layer capacitance C j as a function of bias voltage V D . W EXAMPLE If the zero-bias capacitance of a diffused junction is 3 pF and = 0.5 V, calculate the capacitance with 10 V reverse bias. Assume the doping profile can be approximated by an abrupt junction. From (1.21) 2 1.2.2 Junction Breakdown From Fig. l . lc it can be seen that the maximum electric field in the depletion region occurs at the junction, and for an abrupt junction (1.7) yields a value qN'4 w1 Zmax = -- (1.23) E 1.2 Depletion Region of a pn Junction 7 Substitution of (1.14) in (1.23) gives I - [ ~ ~ N A N D V R 1"' max - E (NA + No) where $o has been neglected. Equation 1.24 shows that the maximum field increases as the doping density increases and the reverse bias increases. Although useful for indicat- ing the functional dependence of %, on other variables, this equation is strictly valid for an ideal plane junction only. Practical junctions tend to have edge effects that cause somewhat higher values of g,,, due to a concentration of the field at the curved edges of the junction. Any reverse-biased pn junction has a small reverse current flow due to the presence of minority-carrier holes and electrons in the vicinity of the depletion region. These are swept across the depletion region by the field and contribute to the leakage current of the junction. As the reverse bias on the junction is increased, the maximum field increases and the carriers acquire increasing amounts of energy between lattice collisions in the depletion region. At a critical field %,., the carriers traversing the depletion region acquire sufficient energy to create new hole-electron pairs in collisions with silicon atoms. This is called the avalanche process and leads to a sudden increase in the reverse-bias leakage current since the newly created carriers are also capable of producing avalanche. The value of %,,, is about 3 X 105 V/cm for junction doping densities in the range of 1015 to 1016 atoms/cm3, but it increases slowly as the doping density increases and reaches about 106 V/cm for doping densities of 1018 atoms/cm3. A typical I-V characteristic for a junction diode is shown in Fig. 1.4, and the effect of avalanche breakdown is seen by the large increase in reverse current, which occurs as the reverse bias approaches the breakdown voltage BV. This corresponds to the maximum field %, approaching %,",. It has been found empirically4 that if the normal reverse bias current of the diode is IR with no avalanche effect, then the actual reverse current near the breakdown voltage is Figure 1.4 Typical I-V characteristic of a junction diode showing avalanche breakdown. 10 Chapter 1 m Models for Integrated-Circuit Active Devices E B C 1 Carrier concentration Emitter Base Collector (4 Figure 1.6 (a) Cross section of a typical npn planar bipolar transistor structure. (b) Idealized tran- sistor structure. (c) Carrier concentrations along the cross section AA' of the transistor in (b). Uni- form doping densities are assumed. (Not to scale.) and thus where p,(x) is the hole concentration in the base and NA is the base doping density that is assumed constant. Equation 1.30 indicates that the hole and electron concentrations are separated by a constant amount and thus pp(x) also varies linearly with distance. Collector current is produced by minority-carrier electrons in the base diffusing in the direction of the concentration gradient and being swept across the collector-base depletion region by the field existing there. The diffusion current density due to electrons in the base is 1.3 Large-Signal Behavior of Bipolar Transistors 11 where D, is the diffusion constant for electrons. From Fig. 1 . 6 ~ If Ic is the collector current and is taken as positive flowing into the collector, it follows from (1.32) that where A is the cross-sectional area of the emitter. Substitution of (1.27) into (1.33) gives where qAD n zc = VBE exp - W B VT VBE' = Is exp - VT and Is is a constant used to describe the transfer characteristic of the transistor in the forward-active region. Equation 1.36 can be expressed in terms of the base doping density by noting thats (see Chapter 2) and substitution of (1.37) in (1.36) gives where QB = WBNA is the number of doping atoms in the base per unit area of the emitter and ni is the intrinsic carrier concentration in silicon. In this form (1.38) applies to both uniform- and nonuniform-base transistors and D, has been replaced by D,, which is an average effective value for the electron diffusion constant in the base. This is necessary for nonuniform-base devices because the diffusion constant is a function of impurity concentration. Typical values of Is as given by (1.38) are from 10-l4 to 10-l6 A. Equation 1.35 gives the collector current as a function of base-emitter voltage. The base current IB is also an important parameter and, at moderate current levels, consists of two major components. One of these ( I B l ) represents recombination of holes and electrons in the base and is proportional to the minority-carrier charge Q, in the base. From Fig. 1.6c, the minority-carrier charge in the base is and we have 12 Chapter 1 4 Models for Integrated-Circuit Active Devices where rb is the minority-carrier lifetime in the base. IB1 represents a flow of majority holes from the base lead into the base region. Substitution of (1.27) in (1.40) gives The second major component of base current (usually the dominant one in integrated- circuit npn devices) is due to injection of holes from the base into the emitter. This current component depends on the gradient of minority-carrier holes in the emitter and is9 where D, is the diffusion constant for holes and L, is the diffusion length (assumed small) for holes in the emitter. pnE(0) is the concentration of holes in the emitter at the edge of the depletion region and is If ND is the donor atom concentration in the emitter (assumed constant), then The emitter is deliberately doped much more heavily than the base, making ND large and p n ~ o small, so that the base-current component, IB2, is minimized. Substitution of (1.43) and (1.44) in (1.42) gives qAD n2 VBE IB2 = -- P exp - The total base current, IB, is the sum of ZB1 and IB2: Although this equation was derived assuming uniform base and emitter doping, it gives the correct functional dependence of IB on device parameters for practical double-diffused nonuniform-base devices. Second-order components of ZB, which are important at low current levels, are considered later. Since Ic in (1.35) and IB in (1.46) are both proportional to exp(VBE/VT) in this anal- ysis, the base current can be expressed in terms of collector current as where PF is the forward current gain. An expression for PF can be calculated by substi- tuting (1.34) and (1.46) in (1.47) to give where (1.37) has been substituted for npo. Equation 1.48 shows that PF is maximized by minimizing the base width WB and maximizing the ratio of emitter to base doping 1.3 Large-Signal Behavior of Bipolar Transistors 15 Carrier concentration A I Collector depletion I region widens due to AV,, I I Emitter Base -depletion 4 region I I I I I , Figure 1.9 Effect of in- creases in VCE on the B ~ollector collector depletion re- gion and base width of a bipolar transistor. For a uniform-base transistor QB = WENA, and (1.54) becomes Note that since the base width decreases as VCE increases, d WBldVcE in (1.55) is negative and thus dIcldVCE is positive. The magnitude of d WBldVcE can be calculated from (1.18) for a uniform-base transistor. This equation predicts that dWB/dVcE is a function of the bias value of VCE, but the variation is typically small for a reverse-biased junction and dWsldVcE is often assumed constant. The resulting predictions agree adequately with experimental results. Equation 1.55 shows that dIcldVcs is proportional to the collector-bias current and inversely proportional to the transistor base width. Thus narrow-base transistors show a greater dependence of Ic on VCE in the forward-active region. The dependence of dIcldVcE on Ic results in typical transistor output characteristics as shown in Fig. 1.10. In accordance with the assumptions made in the foregoing analysis, these characteristics are shown for constant values of VBE. However, in most integrated-circuit transistors the base current is dependent only on VBE and not on VCE, and thus constant-base-current characteristics can often be used in the following calculation. The reason for this is that the base current is usually dominated by the IB2 component of (1.45), which has no de- pendence on VCE. Extrapolation of the characteristics of Fig. 1.10 back to the VCE axis gives an intercept V A called the Early voltage, where Substitution of (1.55) in (1 S6) gives which is a constant, independent of Ic. Thus all the characteristics extrapolate to the same point on the VCE axis. The variation of Ic with VCE is called the Early effect, and V A is a common model parameter for circuit-analysis computer programs. Typical values of V A 16 Chapter 1 Models for integrated-Circuit Active Devices Figure 1.10 Bipolar transistor output characteristics showing the Early voltage, VA. for integrated-circuit transistors are 15 to 100 V. The inclusion of Early effect in dc bias calculations is usually limited to computer analysis because of the complexity introduced into the calculation. However, the influence of the Early effect is often dominant in small- signal calculations for high-gain circuits and this point will be considered later. Finally, the influence of Early effect on the transistor large-signal characteristics in the forward-active region can be represented approximately by modifying (1.35) to Ic = Is 1 + - exp - ( v:,.) 7: This is a common means of representing the device output characteristics for computer simulation. 1.3.3 Saturation and Inverse-Active Regions Saturation is a region of device operation that is usually avoided in analog circuits because the transistor gain is very low in this region. Saturation is much more commonly encoun- tered in digital circuits, where it provides a well-specified output voltage that represents a logic state. In saturation, both emitter-base and collector-base junctions are forward biased. Con- sequently, the collector-emitter voltage VCE is quite small and is usually in the range 0.05 to 0.3 V. The carrier concentrations in a saturated npn transistor with uniform base doping are shown in Fig. 1.11. The minority-carrier concentration in the base at the edge of the depletion region is again given by (1.28) as but since VBC is now positive, the value of np(WB) is no longer negligible. Consequently, changes in VCE with VBE held constant (which cause equal changes in V B C ) directly affect np(We). Since the collector current is proportional to the slope of the minority-carrier con- centration in the base [see (1.3 l ) ] , it is also proportional to [np(0) - nP(WB)] from Fig. 1.11. Thus changes in np(WB) directly affect the collector current, and the collector node of the transistor appears to have a low impedance. As VCE is decreased in saturation with VBE held constant, VBC increases, as does np(WB) from (1.59). Thus from Fig. 1 .l 1 the collector 1.3 Large-Signal Behavior of Bipolar Transistors 17 I l Pnc P ~ E ,X Emitter Base I l ! Collector Figure 1.1 1 Carrier concentrations in a saturated npn transistor. (Not to scale.) current decreases because the slope of the carrier concentration decreases. This gives rise to the saturation region of the Ic - VCE characteristic shown in Fig. 1.12. The slope of the Ic - VCE characteristic in this region is largely determined by the resistance in series with the collector lead due to the finite resistivity of the n-type collector material. A useful model for the transistor in this region is shown in Fig. 1.13 and consists of a fixed voltage source to represent VB,qon), and a fixed voltage source to represent the collector-emitter voltage VCqsat). A more accurate but more complex model includes a resistor in series with the collector. This resistor can have a value ranging from 20 to 500 Cl, depending on the device structure. An additional aspect of transistor behavior in the saturation region is apparent from Fig. 1.11. For a given collector current, there is now a much larger amount of stored charge in the base than there is in the forward-active region. Thus the base-current contribution represented by (1.41) will be larger in saturation. In addition, since the collector-base junc- tion is now forward biased, there is a new base-current component due to injection of carriers from the base to the collector. These two effects result in a base current IB in sat- uration, which is larger than in the forward-active region for a given collector current Ic. Ratio Ic/IB in saturation is often referred to as the forced P and is always less than P F . As the forced P is made lower with respect to P F , the device is said to be more heavily saturated. The minority-carrier concentration in saturation shown in Fig. 1.11 is a straight line joining the two end points, assuming that recombination is small. This can be represented as a linear superposition of the two dotted distributions as shown. The justification for this is that the terminal currents depend linearly on the concentrations np(0) and np(WB). This picture of device carrier concentrations can be used to derive some general equations de- scribing transistor behavior. Each of the distributions in Fig. l . l l is considered separately and the two contributions are combined. The emitter current that would result from npl (X) above is given by the classical diode equation IEF = -IES exp - - 1 ( ? ) where IES is a constant that is often referred to as the saturation current of the junction (no connection with the transistor saturation previously described). Equation 1.60 predicts that the junction current is given by IEF = IES with a reverse-bias voltage applied. However, Chapter 1 Models for Integrated-Circuit Active Devices Substitution of (1.68) in (1.65) gives where and Ico is the collector-base leakage current with the emitter open. Although Ico is given theoretically by (1.69a), in practice, surface leakage effects dominate when the collector- base junction is reverse biased and Ico is typically several orders of magnitude larger than the value given by (1.69a). However, (1.69) is still valid if the appropriate measured value for Ico is used. Typical values of Ico are from 10-l0 to 10-l2 A at 25OC, and the magnitude doubles about every 8•‹C. As a consequence, these leakage terms can become very significant at high temperatures. For example, consider the base current IB. From Fig. 1.5 this is r, = -(lc + I E ) (1.70) If IE is calculated from (1.69) and substituted in (1.70), the result is But from ( 1 SO) and use of (1.72) in (1.7 1) gives Since the two terms in (1.73) have opposite signs, the effect of Ico is to decrease the magnitude of the external base current at a given value of collector current. EXAMPLE If Ico is 10-l0 A at 24"C, estimate its value at 120•‹C. Assuming that Ico doubles every 8"C, we have IC0(12O0C) = 10-l0 X 212 = 0.4 pA 1.3.4 Transistor Breakdown Voltages In Section 1.2.2 the mechanism of avalanche breakdown in a pn junction was described. Similar effects occur at the base-emitter and base-collector junctions of a transistor and these effects limit the maximum voltages that can be applied to the device. First consider a transistor in the common-base configuration shown in Fig. 1.14~ and supplied with a constant emitter current. Typical Ic - VCB characteristics for an npn tran- sistor in such a connection are shown in Fig. 1.14b. For IE = 0 the collector-base junction breaks down at a voltage BVcBo, which represents collector-base breakdown with the emitter open. For finite values of IE, the effects of avalanche multiplication are apparent for values of VcB below BVcBo. In the example shown, the effective common-base current 1.3 Large-Signal Behavior of Bipolar Transistors 21 I I transistor connection. (a) BVCBO Test circuit. (b) Zc - VCB (b) characteristics. gain a~ = Ic/IE becomes larger than unity for values of VCB above about 60 V. Operation in this region (but below BVcBo) can, however, be safely undertaken if the device power dissipation is not excessive. The considerations of Section 1.2.2 apply to this situation, and neglecting leakage currents, we can calculate the collector current in Fig. 1 . 1 4 ~ as where M is defined by (1.26) and thus One further point to note about the common-base characteristics of Fig. 1.14b is that for low values of VcB where avalanche effects are negligible, the curves show very little of the Early effect seen in the common-emitter characteristics. Base widening still occurs in this configuration as VcB is increased, but unlike the common-emitter connection, it produces little change in Ic. This is because IE is now fixed instead of VBE or IB, and in Fig. 1.9, this means the slope of the minority-carrier concentration at the emitter edge of the base is fixed. Thus the collector current remains almost unchanged. Now consider the effect of avalanche breakdown on the common-emitter characteris- tics of the device. Typical characteristics are shown in Fig. 1.12, and breakdown occurs at a value BVcEo, which is sometimes called the sustaining voltage LVcEo. As in previous cases, operation near the breakdown voltage is destructive to the device only if the current (and thus the power dissipation) becomes excessive. The effects of avalanche breakdown on the common-emitter characteristics are more complex than in the common-base configuration. This is because hole-electron pairs are produced by the avalanche process and the holes are swept into the base, where they ef- fectively contribute to the base current. In a sense the avalanche current is then amplzjied 22 Chapter 1 Models for Integrated-Circuit Active Devices by the transistor. The base current is still given by IB = -(Ic + IE) Equation 1.74 still holds, and substitution of this in (1.76) gives where Equation 1.77 shows that lc approaches infinity as MaF approaches unity. That is, the effective approaches infinity because of the additional base-current contribution from the avalanche process itself. The value of BVcEo can be determined by solving If we assume that VCR = V C ~ , this gives and this results in and thus Equation 1.81 shows that BVcEo is less than BVcBo by a substantial factor. However, the value of BVcBo, which must be used in (1.81), is the plane junction breakdown of the collector-base junction, neglecting any edge effects. This is because it is only collector- base avalanche current actually under the emitter that is amplified as described in the pre- vious calculation. However, as explained in Section 1.2.2, the measured value of BVcso is usually determined by avalanche in the curved region of the collector, which is remote from the active base. Consequently, for typical values of PF = 100 and n = 4, the value of BVcEo is about one-half of the measured BVcso and not 30 percent as (1.81) would indicate. Equation 1 .8 1 explains the shape of the breakdown characteristics of Fig. 1.12 if the dependence of PF on collector current is included. As VCE is increased from zero with IB = 0, the initial collector current is approximately P F I C o from (1.73); since Ico is typ- ically several picoamperes, the collector current is very small. As explained in the next section, PF is small at low currents, and thus from (1.81) the breakdown voltage is high. However, as avalanche breakdown begins in the device, the value of Ic increases and thus PF increases. From (1.81) this causes a decrease in the breakdown voltage and the characteristic bends back as shown in Fig. 1.12 and exhibits a negative slope. At higher collector currents, PF approaches a constant value and the breakdown curve with Is = 0 becomes perpendicular to the VCE axis. The value of VCE in this region of the curve is 1.3 Large-Signal Behavior of Bipolar Transistors 25 Figure 1 .l6 Base and collector currents of a bipolar transistor plotted on a log scale versus VBE on a linear scale. The distance between I * "BE the curves is a direct (linear scale) measure of 1n p F . At very low collector currents, where (1.84) dominates the base current, the current gain can be calculated from (1.82) and (1.84) as Substitution of (1.82) in (1 M ) gives If m = 2, then (1.86) indicates that PF is proportional to f i a t very low collector currents. At high current levels, the base current IB tends to follow the relationship of (1.83), and the decrease in PF in region I11 is due mainly to a decrease in Ic below the value given by (1 32). (In practice the measured curve of IB versus VBE in Fig. 1.16 may also deviate from a straight line at high currents due to the influence of voltage drop across the base resistance.) The decrease in Ic is due partly to the effect of high-level injection, and at high current levels the collector current approaches7 VBE Ic = IsH exp - 2 VT The current gain in this region can be calculated from (1 37) and (1.83) as Substitution of (1.87) in (1.88) gives Thus PF decreases rapidly at high collector currents. 26 Chapter 1 Models for Integrated-Circuit Active Devices In addition to the effect of high-level injection, the value of PF at high cutrents is also decreased by the onset of the Kirk effect,13 which occurs when the minority-carrier con- centration in the collector becomes comparable to the donor-atom doping density. The base region of the transistor then stretches out into the collector and becomes greatly enlarged. 1.4 Small-Signal Models of Bipolar Transistors Analog circuits often operate with signal levels that are small compared to the bias currents and voltages in the circuit. In these circumstances, incremental or small-signal models can be derived that allow calculation of circuit gain and terminal impedances without the ne- cessity of including the bias quantities. A hierarchy of models with increasing complexity can be derived, and the more complex ones are generally reserved for computer analysis. Part of the designer's skill is knowing which elements of the model can be omitted when performing hand calculations on a particular circuit, and this point is taken up again later. Consider the bipolar transistor in Fig. 1 .17~ with bias voltages VBE and Vcc applied as shown. These produce a quiescent collector current, Ic, and a quiescent base current, IB , and the device is in the forward-active region. A small-signal input voltage vi is applied in series with V B E and produces a small variation in base current ib and a small variation in collector current i,. Total values of base and collector currents are Ib and I,, respectively, and thus Ib = ( IB + ib) and I, = ( I c + i,). The carrier concentrations in the base of the transistor corresponding to the situation in Fig. 1 .17~ are shown in Fig. 1.17b. With only Carrier concentration t " B E Y n~(0) = 'PO exp F 4 Qe Emitter Base /' Emitter depletion region (b) Collector I depletion I region j -X Collector Figure 1.17 Effect of a small-signal input voltage applied to a bipolar transistor. (a) Circuit schematic. (b) Corresponding changes in carrier concentrations in the base when the device is in the forward-active region. 1.4 Small-Signal Models of Bipolar Transistors 27 bias voltages applied, the carrier concentrations are given by the solid lines. Application of the small-signal voltage vi causes n,(O) at the emitter edge of the base to increase, and produces the concentrations shown by the dotted lines. These pictures can now be used to derive the various elements in the small-signal equivalent circuit of the bipolar transistor. 1.4.1 Transconductance The transconductance is defined as Since we can write A I c = grnAVBE and thus = gmvi (1.90) The value of g, can be found by substituting (1.35) in (1 39 ) to give The transconductance thus depends linearly on the bias current Ic and is 38 mAN for Ic = 1 mA at 25•‹C for any bipolar transistor of either polarity (npn or pnp), of any size, and made of any material (Si, Ge, GaAs). To illustrate the limitations on the use of small-signal analysis, the foregoing relation will be derived in an alternative way. The total collector current in Fig. 1 . 1 7 ~ can be calculated using (1.35) as I , = Is exp VBE + vi VBE vi = Is exp -exp - VT VT VT But the collector bias current is VBE Ic = Is exp - VT and use of (1.93) in (1.92) gives V i Ic = Ic exp - (1.94) VT If vi < V T , the exponential in (1.94) can be expanded in a power series, Now the incremental collector current is ic = I , - Ic 30 Chapter 1 Models for Integrated-Circuit Active Devices Substitution of (1.55) and (1.57) in ( 1 . 1 l 1 ) gives AVCE - V A AI, I, - ro where V A is the Early voltage and r, is the small-signal output resistance of the transistor. Since typical values of VA are 50 to 100 V, corresponding values of r, are 50 to 100 ki2 for Ic = 1mA. Note that r, is inversely proportional to I,, and thus r, can be related to g,, as are many of the other small-signal parameters. where If V A = 100 V, then 77 = 2.6 X 1oP4 at 25OC. Note that llr, is the slope of the output characteristics of Fig. 1.10. 1.4.5 Basic Small-Signal Model of the Bipolar Transistor Combination of the above small-signal circuit elements yields the small-signal model of the bipolar transistor shown in Fig. 1.18. This is valid for both npn and pnp devices in the forward-active region and is called the hybrid-.rr model. Collector, base, and emitter nodes are labeled C, B and E, respectively. The elements in this circuit are present in the equivalent circuit of any bipolar transistor and are specified by relatively few parameters (P , TF, 7, I,). Note that in the evaluation of the small-signal parameters for pnp transistors, the magnitude only of Ic is used. In the following sections, further elements are added to this model to account for parasitics and second-order effects. 1.4.6 Collector-Base Resistance Consider the effect of variations in VCE on the minority charge in the base as illustrated in Fig. 1.9. An increase in VCE causes an increase in the collector depletion-layer width and consequent reduction of base width. This causes a reduction in the total minority-carrier charge stored in the base and thus a reduction in base current IB due to a reduction in IB1 given by (1.40). Since an increase AVcE in VCE causes a decrease AIB in Ie, this effect can be modeled by inclusion of a resistor r, from collector to base of the model of Fig. 1.18. If VBE is assumed held constant, the value of this resistor can be determined as follows. P 1 q k Figure 1.18 Basic bipolar transistor r I r = g , , r o = - , g , = - - ,C,=T,~ , 78 , kT small-signal equivalent circuit. 1.4 Small-Signal Models of Bipolar Transistors 3 1 Substitution of (1.112) in (1.115) gives If the base current IB is composed entirely of component I B ~ , then (1.107) can be used in (1.116) to give This is a lower limit for r,. In practice, IB1 is typically less than 10 percent of IB [compo- nent IB2 from (1 . a ) dominates] in integrated npn transistors, and since IB1 is very small, the change AIBl in lBl for a given AVCE and AIc is also very small. Thus a typical value for r, is greater than 10Por,. For lateral pnp transistors, recombination in the base is more significant, and r, is in the range 2Por, to 5Poro 1.4.7 Parasitic Elements in the Small-Signal Model The elements of the bipolar transistor small-signal equivalent circuit considered so far may be considered basic in the sense that they arise directly from essential processes in the de- vice. However, technological limitations in the fabrication of transistors give rise to a number of parasitic elements that must be added to the equivalent circuit for most integrated-circuit transistors. A cross section of a typical npn transistor in a junction- isolated process is shown in Fig. 1.19. The means of fabricating such devices is described in Chapter 2. As described in Section 1.2, all pn junctions have a voltage-dependent capacitance as- sociated with the depletion region. In the cross section of Fig. 1.19, three depletion-region capacitances can be identified. The base-emitter junction has a depletion-region capaci- tance Cj, and the base-collector and collector-substrate junctions have capacitances C, and C,., respectively. The base-emitter junction closely approximates an abrupt junction due to the steep rise of the doping density caused by the heavy doping in the emitter. Thus the variation of Cj, with bias voltage is well approximated by (1.21). The collector- base junction behaves like a graded junction for small bias voltages since the doping den- sity is a function of distance near the junction. However, for larger reverse-bias values (more than about a volt), the junction depletion region spreads into the collector, which is @l Substrate Figure 1.19 Integrated-circuit npn bipolar transistor structure showing parasitic elements. (Not to scale.) 32 Chapter 1 Models for Integrated-Circuit Active Devices uniformly doped, and thus for devices with thick collectors the junction tends to behave like an abrupt junction with uniform doping. Many modem high-speed processes, how- ever, have very thin collector regions (of the order of one micron), and the collector deple- tion region can extend all the way to the buried layer for quite small reverse-bias voltages. When this occurs, both the depletion region and the associated capacitance vary quite slowly with bias voltage. The collector-base capacitance C, thus tends to follow (1.22) for very small bias voltages and (1.21) for large bias voltages in thick-collector devices. In practice, measurements show that the variation of C, with bias voltage for most devices can be approximated by where V is the forward bias on the junction and n is an exponent between about 0.2 and 0.5. The third parasitic capacitance in a monolithic npn transistor is the collector-substrate capacitance C,,, and for large reverse bias voltages this varies according to the abrupt junction equation (1.2 1) for junction-isolated devices. In the case of oxide-isolated devices, however, the deep p diffusions used to isolate the devices are replaced by oxide. The sidewall component of C,, then consists of a fixed oxide capacitance. Equation 1.117a may then be used to model C,,, but a value of n less than 0.5 gives the best approximation. In general, (1.1 17a) will be used to model all three parasitic capacitances with subscripts e, c , and s on n and used to differentiate emitter-base, collector-base, and collector-substrate capacitances, respectively. Typical zero-bias values of these parasitic capacitances for a minimum-size npn transistor in a modern oxide-isolated process are Cjeo -- 10 fF, CPo 21 10 fF, and CCso - 20 fF. Values for other devices are summarized in Chapter 2. As described in Chapter 2, lateral pnp transistors have a parasitic capacitance Cbs from base to substrate in place of C,,. Note that the substrate is always connected to the most negative voltage supply in the circuit in order to ensure that all isolation regions are separated by reverse-biased junctions. Thus the substrate is an ac ground, and all parasitic capacitance to the substrate is connected to ground in an equivalent circuit. The final elements to be added to the small-signal model of the transistor are resis- tive parasitics. These are produced by the finite resistance of the silicon between the top contacts on the transistor and the active base region beneath the emitter. As shown in Fig. 1.19, there are significant resistances rb and r, in series with the base and collector con- tacts, respectively. There is also a resistance re, of several ohms in series with the emitter lead that can become important at high bias currents. (Note that the collector resistance r, is actually composed of three parts labeled r , ~ , r,-, and rC3.) Typical values of these parameters are rb = 50 to 500 a, re, = 1 to 3 a , and r, = 20 to 500 a. The value of rb varies significantly with collector current because of current crowding.15 This occurs at high collector currents where the dc base current produces a lateral voltage drop in the base that tends to forward bias the base-emitter junction preferentially around the edges of the emitter. Thus the transistor action tends to occur along the emitter periphery rather than under the emitter itself, and the distance from the base contact to the active base region is reduced. Consequently, the value of rb is reduced, and in a typical npn transistor, rb may decrease 50 percent as lc increases from 0.1 mA to 10 mA. The value of these parasitic resistances can be reduced by changes in the device struc- ture. For example, a large-area transistor with multiple base and emitter stripes will have a smaller value of rb. The value of r, is reduced by inclusion of the low-resistance buried n+ layer beneath the collector. 1.4 Small-Signal Models of Bipolar Transistors 35 Figure 1.22 Schematic of ac circuit for measurement of f ~ . +- Figure l .23 Small-signal equivalent circuit for the calculation of fT . influence, and we have r, v1 % ii 1 + r,(C, + C,)s If the current fed forward through C, is neglected, 10 gmV1 Substitution of (1.119) in (1.120) gives (1.119) ( l . 120) and thus 10 T (jm) = P 0 li 1 + p,cr + g m jw using (1.110). Now if iolii(jo) is written as p( jw) (the high-frequency, small-signal current gain), then ( l . 122) At high frequencies the imaginary part of the denominator of (1.122) is dominant, and we can write 36 Chapter 1 m Models for Integrated-Circuit Active Devices 1000 - . p, (low frequency value) 100 - Figure 1.24 Magnitude of small-signal ac cur- rent gain Ip(jco)l versus log scale frequency for a typical bipolar transistor. and thus The transistor behavior can be illustrated by plotting IP(jo)l using (1.122) as shown in Fig. 1.24. The frequency wg is defined as the frequency where P ( j o ) is equal to PO/ ,h (3 dB down from the low-frequency value). From (1.122) we have (l . 126) From Fig. 1.24 it can be seen that o~ can be determined by measuring IP(jw)l at some frequency ox where IP(jo)l is falling at 6 dB/octave and using This is the method used in practice, since deviations from ideal behavior tend to occur as (jw )l approaches unity. Thus IP ( j o ) ( is typically measured at some frequency where its magnitude is about 5 or 10, and (1.127) is used to determine w ~ . It is interesting to examine the time constant, TT, associated with w ~ . This is de- fined as and use of (1.124) in (1.128) gives Substitution of (1.11 8) and ( l . 104) in (1.129) gives Equation 1.130 indicates that TT is dependent on Ic (through gm) and approaches a constant value of r~ at high collector bias currents. At low values of Ic, the terms involving C;, and C , dominate, and they cause TT to rise and fT to fall as Ic is decreased. This behavior is illustrated in Fig. 1.25, which is a typical plot of fT versus Ic for an integrated-circuit npn transistor. The decline in fT at high collector currents is not predicted by this simple theory and is due to an increase in TF caused by high-level injection and Kirk effect at high 1.4 Small-Signal Models of Bi~olar Transistors 37 fr GHz Figure 1.25 Typical curve of f~ ver- sus Ic for an npn integrated-circuit transistor with 6 p,m2 emitter area in a high-speed process. currents. These are the same mechanisms that cause a decrease in PF at high currents as described in Section 1.3.5. EXAMPLE A bipolar transistor has a short-circuit, common-emitter current gain at 1 GHz of 8 with Ic = 0.25 mA and 9 with Ic = 1 mA. Assuming that high-level injection effects are negligible, calculate C j , and TF, assuming both are constant. The measured value of C, is 10 fE From the data, values of fT are f ~ , = 8 X 1 = 8GHz at Ic = 0.25 rnA fT2 = 9 X 1 = 9 GHz at Ic = 1 mA Corresponding values of 77. are Using these data in (1.130), we have 19.9 X 10-l2 = 7~ f 104(Cp + Cje) at Ic = 0.25 mA. At Ic = 1 mA we have 17.7 X 10-l2 = + 26(Cp + Cje) Subtraction of (1.132) from (1.13 1) yields C , + Cj, = 28.2 fF Since C, was measured as 10 fF, the value of Cje is given by Cj , 18.2 fF 40 Chapter 1 8 Models for Integrated-Circuit Active Devices When the surface potential in the silicon reaches a critical value equal to twice the Fermi level r$f, a phenomenon known as inversion occur^.'^ The Fermi level 4f is defined as where k is Boltzmann's constant. Also, ni is the intrinsic carrier concentration, which is where E, is the band gap of silicon at T = O•‹K, Nc is the density of allowed states near the edge of the conduction band, and Nv is the density of allowed states near the edge of the valence band, respectively. The Fermi level 4f is usually about 0.3 V. After the potential in the silicon reaches 24f, further increases in gate voltage produce no further changes in the depletion-layer width but instead induce a thin layer of electrons in the depletion layer at the surface of the silicon directly under the oxide. Inversion produces a continuous n-type region with the source and drain regions and forms the conducting channel between source and drain. The conductivity of this channel can be modulated by increases or decreases in the gate-source voltage. In the presence of an inversion layer, and without substrate bias, the depletion region contains a fixed charge density If a substrate bias voltage VS* (positive for n-channel devices) is applied between the source and substrate, the potential required to produce inversion becomes (24f + Vss), and the charge density stored in the depletion region in general is The gate-source voltage VGS required to produce an inversion layer is called the threshold voltage Vt and can now be calculated. This voltage consists of several com- ponents. First, a voltage [24 + (Qb/Cox)] is required to sustain the depletion-layer charge Qb, where C,, is the gate oxide capacitance per unit area. Second, a work-function dif- ference r$, exists between the gate metal and the silicon. Third, positive charge density Qs, always exists in the oxide at the silicon interface. This charge is caused by crystal dis- continuities at the Si - Si02 interface and must be compensated by a gate-source voltage contribution of - Q,s/C,,. Thus we have a threshold voltage where (1.137) and (1.138) have been used, and Vto is the threshold voltage with Vss = 0. The parameter y is defined as 1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 41 and where E ox and to, are the permittivity and the thickness of the oxide, respectively. A typical value of y is 0.5 and Cox = 3.45 fWPm2 for to, = 100 angstroms. In practice, the value of Vro is usually adjusted in processing by implanting additional impurities into the channel region. Extra p-type impurities are implanted iu the channel to set Vto between 0.5 V and 1.5 V for n-channel enhancement devices. By implanting n-type impurities in the channel region, a conducting channel can be formed even for VGS = 0, forming a depletion device with typical values of Vro in the range - 1 V to -4 V. If Q, is the charge density due to the implant, then the threshold voltage given by (1.139) is shifted by approximately Qi/Cox4 The preceding equations can now be used to calculate the large-signal characteris- tics of an n-channel MOSFET. In this analysis, the source is assumed grounded and bias voltages VGS, VDS, and VSB are applied as shown in Fig. 1.28. If VGS > Vr, inversion occurs and a conducting channel exists. The channel conductivity is determined by the vertical electric field, which is controlled by the value of (VGS - Vr). If VDs = 0, the cur- rent ID that flows from drain to source is zero because the horizontal electric field is zero. Nonzero VDs produces a horizontal electric field and causes current ID to flow. The value of the current depends on both the horizontal and the vertical electric fields, explaining the temjeld-efSect transistor. Positive voltage VDs causes the reverse bias from the drain to the substrate to be larger than from the source to substrate, and thus the widest depletion region exists at the drain. For simplicity, however, we assume that the voltage drop along the channel itself is small so that the depletion-layer width is constant along the channel. The drain current ID is where dQ is the incremental channel charge at a distance y from the source in an incre- mental length d y of the channel, and d t is the time required for this charge to cross length dy. The charge d Q is where W is the width of the device perpendicular to the plane of Fig. 1.28 and Qr is the induced electron charge per unit area of the channel. At a distance y along the channel, the voltage with respect to the source is V ( y ) and the gate-to-channel voltage at that point is ~e~letion 1 r e i n Y Y Y + ~ Y \ p-type substrate - 4 - v? Figure 1.28 NMOS device with bias voltages applied. 42 Chapter 1 Models for Integrated-Circuit Active Devices VGS - V ( y ) . We assume this voltage exceeds the threshold voltage Vt. Thus the induced electron charge per unit area in the channel is Also, where vd is the electron drift velocity at a distance y from the source. Combining (1.144) and (1.146) gives The drift velocity is determined by the horizontal electric field. When the horizontal elec- tric field % ( y ) is small, the drift velocity is proportional to the field and where the constant of proportionality p, is the average electron mobility in the channel. In practice, the mobility depends on both the temperature and the doping level but is almost constant for a wide range of normally used doping levels. Also, p, is sometimes called the surface mobility for electrons because the channel forms at the surface of the silicon. Typical values range from about 500 cm2/(v-S) to about 700 cm2/(v-S), which are much less than the mobility of electrons in the bulk of the silicon (about 1400 cm2N-S) because surface defects not present in the bulk impede the flow of electrons in MOS transistors.17 The electric field % ( y ) is where d V is the incremental voltage drop along the length of channel d y at a distance y from the source. Substituting (1.145), (1.148), and (1.149) into (1.147) gives Separating variables and integrating gives Carrying out this integration gives where FnEox k' = pnCox = - (1.153) t ox When VDs << 2(VGs - V,), (1.152) predicts that ID is approximately proportional to VDs. This result is reasonable because the average horizontal electric field in this case is VD~/L, and the average drift velocity of electrons is proportional to the average field when the field is small. Equation 1.152 is important and describes the I-V characteristics of an MOS transistor, assuming a continuous induced channel. A typical value of k' for to, = 100 angstroms is about 200 FAN2 for an n-channel device. 1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 45 of VDs is shown in Fig. 1.29. For depletion n-channel MOS devices, V, is negative, and ID is nonzero even for VGS = 0. For PMOS devices, all polarities of voltages and currents are reversed. The results derived above can be used to form a large-signaI model of the NMOS transistor in saturation. The model topology is shown in Fig. 1.30, where ID is given by (1.152) in the triode region and (1.157) in saturation, ignoring the effect of channel-length modulation. To include the effect of channel-length modulation, (1.159) or (1.165) should be used instead of (1.157) to find the drain current in saturation. 1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors Notice that the meaning of the word saturation for MOS transistors is quite different than for bipolar transistors. Saturation in bipolar transistors refers to the region of operation where both junctions are forward biased and the collector-emitter voltage is approximately constant or saturated. On the other hand, saturation in MOS transistors refers to the region of operation where the channel is attached only to the source but not to the drain and the current is approximately constant or saturated. To avoid confusion, the term active region will be used in this book to describe the flat region of the MOS transistor characteristics, as shown in Fig. 1.29. This wording is selected to form a link between the operation of MOS and bipolar transistors. This link is summarized in the table of Fig. 1.31, which reviews the operating regions of npn bipolar and n-channel MOS transistors. When the emitter junction is forward biased and the collector junction is reverse bi- ased, bipolar transistors operate in the forward-active region. They operate in the reverse- active region when the collector junction is forward biased and the emitter junction is reverse biased. This distinction is important because integrated-circuit bipolar transistors are typically not symmetrical in practice; that is, the collector operates more efficiently as a collector of minority carriers than as an emitter. Similarly, the emitter operates more efficiently as an emitter of minority carriers than as a collector. One reason for this asym- metry is that the collector region surrounds the emitter region in integrated-circuit bipolar transistors, as shown in Fig. 1.19. A consequence of this asymmetry is that the current gain in the forward-active region PF is usually much greater than the current gain in the reverse-active region P R . - o l J Figure 1.30 Large-signal model for the NMOS S transistor. l npn Bipolar Transistor I n-channel MOS Transistor l Figure 1.3 1 Operating regions of npn bipolar and n-channel MOS transistors. Region VBE VBC Cutoff v B ~ ( o n ) < V B C ( ~ ~ ) Forward Active 2 VBECon) < VBC(on) Reverse Active < VBE(on) 2 V R ~ ( ~ ~ ) Saturation 2 VBE(O~) 2 VBC(O~) Region VGS VGD Cutoff c vl < vt Saturation(Active) 2 V, < vt Saturation(Active) < V, m V, Triode r V, 2 V, 1 46 Chapter 1 Models for Integrated-Circuit Active Devices In contrast, the source and drain of MOS transistors are completely interchangeable based on the preceding description. (In practice, the symmetry is good but not perfect.) Therefore, distinguishing between the forward-active and reverse-active regions of oper- ation of an MOS transistor is not necessary. Figure 1.31 also shows that npn bipolar transistors operate in cutoff when both junc- tions are reversed biased. Similarly, MOS transistors operate in cutoff when the gate is biased so that inversion occurs at neither the source nor the drain. Furthermore, npn tran- sistors operate in saturation when both junctions are forward biased, and MOS transistors operate in the triode region when the gate is biased so that the channel is connected to both the source and the drain. Therefore, this comparison leads us to view the voltage required to invert the surface of an MOS transistor as analogous to the voltage required to forward bias a pn junction in a bipolar transistor. To display this analogy, we will use the circuit symbols in Fig. 1 . 3 2 ~ to represent MOS transistors. These symbols are inten- tionally chosen to appear similar to the symbols of the corresponding bipolar transistors. In bipolar-transistor symbols, the arrow at the emitter junction represents the direction of current flow when the emitter junction is forward biased. In MOS transistors, the pn junc- tions between the source and body and the drain and body are reverse biased for normal operation. Therefore, the arrows in Fig. 1 . 3 2 ~ do not indicate pn junctions. Instead they indicate the direction of current flow when the terminals are biased so that the terminal labeled as the drain operates as the drain and the terminal labeled as the source operates as the source. In NMOS transistors, the source is the source of electrons; therefore, the source operates at a lower voltage than the drain, and the current flows in a direction op- posite that of the electrons in the channel. In PMOS transistors, the source is the source of holes; therefore, the source operates at a higher voltage than the drain, and the current flows in the same direction as the holes in the channel. In CMOS technology, one device type is fabricated in the substrate, which is common to all devices, invariably connected to a dc power-supply voltage, and usually not shown on the circuit diagram. The other device type, however, is fabricated in separate isolation n-channel p-channel (4 S n-channel p-channel n-channel p-channel Figure 1.32 (a) NMOS and PMOS symbols used in CMOS circuits. (b) NMOS and PMOS sym- bols used when the substrate connection is nonstandard. (c) Depletion MOS device symbols. l 1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 47 regions called wells, which may or may not be connected together and which may or may not be connected to a power-supply voltage. If these isolation regions are connected to the appropriate power supply, the symbols of Fig. 1 . 3 2 ~ will be used, and the substrate connection will not be shown. On the other hand, if the individual isolation regions are connected elsewhere, the devices will be represented by the symbols of Fig. 1.32b, where the substrate is labeled B. Finally, symbols for depletion-mode devices, for which a channel forms for VGS = 0 , are shown in Fig. 1.32~. 1 S.3 Decomposition of Gate-Source Voltage The gate-source voltage of a given MOS transistor is usually separated into two parts: the threshold, V,, and the voltage over the threshold, VGS - Vt. We will refer to this latter part of the gate-source voltage as the overdrive. This decomposition is used because these two components of the gate-source voltage have different properties. Assuming square-law behavior as in (1.157), the overdrive is Since the transconductance parameter k' is proportional to mobility, and since mobil- ity falls with increasing temperature, the overdrive rises with temperature. In contrast, the next section shows that the threshold falls with increasing temperature. Furthermore, (1.140) shows that the threshold depends on the source-body voltage, but not on the cur- rent; (1.166) shows that the overdrive depends directly on the current, but not on the source-body voltage. 1.5.4 Threshold Temperature Dependence Assume that the source-body voltage is zero. Substituting (1. 138) into (1.139) gives Assume that +,, Qss, and C,, are independent of temperature.19 Then differentiating (1.167) gives Substituting (1.136) into (1.135) gives Assume both N, and N, are independent of temperature.20 Then differentiating (1.169) gives 50 Chapter 1 Models for Integrated-Circuit Active Devices t Id = ID + id -- - -- "DD Figure 1.33 Schematic of an MOS transistor - with biasing. 1.6.1 Transconductance Assuming square-law operation, the transconductance from the gate can be determined from (1.165) by differentiating. If AVDs << 1, (1.179) simplifies to Unlike the bipolar transistor, the transconductance of the MOS transistor is propor- tional to the square root of the bias current and depends on device geometry (oxide thick- ness via k' and WIL). Another key difference between bipolar and MOS transistors can be seen by calculating the ratio of the transconductance to the current. Using (1.157) and (1.180) for MOS transistors shows that Also, for bipolar transistors, (1.91) shows that At room temperature, the thermal voltage VT is about equal to 26 mV. In contrast, the over- drive V, for MOS transistors in many applications is chosen to be approximately several hundred mV so that MOS transistors are fast enough for the given application. (Section 1.6.8 shows that the transition frequency fr of an MOS transistor is proportional to the overdrive.) Under these conditions, the transconductance per given current is much higher for bipolar transistors than for MOS transistors. One of the key challenges in MOS analog circuit design is designing high-quality analog circuits with a low transconductance-to- current ratio. The transconductance calculated in (1.180) is valid for small-signal analysis. To de- termine the limitation on the use of small-signal analysis, the change in the drain current resulting from a change in the gate-source voltage will be derived from a large-signal standpoint. The total drain current in Fig. 1.33 can be calculated using (1.157) as 1.6 Small-Signal Models of MOS Transistors 5 1 Substituting (1.157) in (1.183) gives Rearranging (1.184) gives If the magnitude of the small-signal input [vi/ is much less than twice the overdrive defined in (1.166), substituting ( l . 180) into (1.185) gives id = gmvi (1.186) In particular, if lvil = lAvGsl is less than 20 percent of the overdrive, the small-signal analysis is accurate within about 10 percent. 1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance If C,, is the oxide capacitance per unit area from gate to channel, then the total capacitance under the gate is C,, W L . This capacitance is intrinsic to the device operation and mod- els the gate control of the channel conductance. In the triode region of device operation, the channel exists continuously from source to drain, and the gate-channel capacitance is usually lumped into two equal parts at the drain and source with In the saturation or active region, however, the channel pinches off before reaching the drain, and the drain voltage exerts little influence on either the channel or the gate charge. As a consequence, the intrinsic portion of Cgd is essentially zero in the saturation region. To calculate the value of the intrinsic part of C,, in the saturation or active region, we must calculate the total charge QT stored in the channel. This calculation can be carried out by substituting (1.145) into (1.144) and integrating to obtain L (1.188) Solving (1.150) for d y and substituting into (1.188) gives where the limit y = L corresponds to V = (VGS - V t ) in the saturation or active region. Solution of (1.189) and use of (1.153) and (1.157) gives 2 QT = S w L c o ~ ( v ~ ~ - vt) (1.190) Therefore, in the saturation or active region, ~ Q T 2 C,, = -= -WLC,, ~ V G S 3 and c,, = 0 52 Chapter 1 Models for Integrated-Circuit Active Devices 1.6.3 Input Resistance The gate of an MOS transistor is insulated from the channel by the Si02 dielectric. As a result, the low-frequency gate current is essentially zero and the input resistance is essentially infinite. This characteristic is important in some circuits such as sample-and- hold amplifiers, where the gate of an MOS transistor can be connected to a capacitor to sense the voltage on the capacitor without leaking away the charge that causes that voltage. In contrast, bipolar transistors have small but nonzero base current and finite input resistance looking into the base, complicating the design of bipolar sample-and- hold amplifiers. 1.6.4 Output Resistance In Section 1.5.1, the effect of changes in drain-source voltage on the large-signal char- acteristics of the MOS transistor was described. Increasing drain-source voltage in an n-channel MOS transistor increases the width of the depletion region around the drain and reduces the effective channel length of the device in the saturation or active re- gion. This effect is called channel-length modulation and causes the drain current to increase when the drain-source voltage is increased. From that treatment, we can calcu- late the change in the drain current AID arising from changes in the drain-source voltage AVDs as Substitution of (1.161), (1.163), and (1.164) in (1.193) gives where VA is the Early voltage, A is the channel-length modulation parameter, ID is the drain current without channel-length modulation given by (1.157), and r, is the small- signal output resistance of the transistor. 1.6.5 Basic Small-Signal Model of the MOS Transistor Combination of the preceding small-signal circuit elements yields the small-signal model of the MOS transistor shown in Fig. 1.34. This model was derived for n-channel transistors in the saturation or active region and is called the hybrid-.rr model. Drain, gate, and source nodes are labeled D, G, and S, respectively. When the gate-source voltage is increased, the model predicts that the incremental current id flowing from drain to source increases. Since the dc drain current ID also flows from drain to source in an n-channel transistor, Figure 1.34 Basic small-signal model of an MOS transistor in the saturation or active region. 1.6 Small-Signal Models of MOS Transistors 55 These capacitances are proportional to the source and drain region areas (including side- walls). Since the channel is attached to the source in the saturation or active region, CXb also includes depletion-region capacitance from the induced channel to the body. A de- tailed analysis of the channel-body capacitance is given in T ~ i v i d i s . ~ ~ In practice, C,, and Cgd, given in (1.187) for the triode region of operation and in (1.191) and (1.192) for the saturation or active region, are increased due to parasitic oxide capacitances arising from gate overlap of the source and drain regions. These overlap capacitances Col are shown in Fig. 1.35a, and their values are calculated in Chapter 2. Capacitance Cgb between gate and body or substrate models parasitic oxide capaci- tance between the gate-contact material and the substrate outside the active-device area. This capacitance is independent of the gate-body voltage and models coupling from polysilicon and metal interconnects to the underlying substrate, as shown by the shaded regions in the top view of Fig. 1.35b. Parasitic capacitance of this type underlies all polysilicon and metal traces on integrated circuits. Such parasitic capacitance should be taken into account when simulating and calculating high-frequency circuit and device performance. Typical values depend on oxide thicknesses. With a silicon dioxide thick- ness of 100 A , the capacitance is about 3.45 fF per square micron. Fringing capacitance becomes important for lines narrower in width than several microns. Parasitic resistance in series with the source and drain can be used to model the nonzero resistivity of the contacts and diffusion regions. In practice, these resistances are often ignored in hand calculations for simplicity but included in computer simulations. These parasitic resistances have an inverse dependence on channel width W. Typical val- ues of these resistances are 50 Cl to 100 Cl for devices with W of about 1 km. Similar parasitic resistances in series with the gate and body terminals are sometimes included but often ignored because very little current flows in these terminals, especially at low frequencies. The small-signal model including capacitive parasitics but ignoring resistive parasitics is shown in Fig. 1.36. 1.6.8 MOS Transistor Frequency Response As for a bipolar transistor, the frequency capability of an MOS transistor is usually spec- ified by finding the transition frequency f ~ . For an MOS transistor, f~ is defined as the Figure 1.36 Small-signal MOS transistor equivalent circuit. 56 Chapter 1 Models for Integrated-Circuit Active Devices Figure 1.37 Circuits for calculating the fT of an MOS transistor: (a) ac schematic and (b) small- signal equivalent. frequency where the magnitude of the short-circuit, common-source current gain falls to unity. Although the dc gate current of an MOS transistor is essentially zero, the high- frequency behavior of the transistor is controlled by the capacitive elements in the small- signal model, which cause the gate current to increase as frequency increases. To calculate fT , consider the ac circuit of Fig. 1.37~ and the small-signal equivalent of Fig. 1.37b. Since v,b = vds = 0, gmb, ro, Csb, and Cdb have no effect on the calculation and are ignored. The small-signal input current ii is If the current fed forward through Cgd is neglected, Solving (1.203) for v,, and substituting into (1.204) gives To find the frequency response, we set s = j w . Then The magnitude of the small-signal current gain is unity when Therefore, Assume the intrinsic device capacitance C,, is much greater than (Cgb + Cgd). Then sub- stituting (1.180) and (1.191) into (1.208) gives Comparison of this equation with the intrinsic fT of a bipolar transistor when parasitic depletion-layer capacitance is neglected leads to an interesting result. From (1.128) and (1.130) with TF >> (C j , + CCL)Igm, 1.6 Small-Signal Models of MOS Transistors 57 Substituting from (1.99) for TF and using the Einstein relationship Dnlpn = kTlq = V r , we find for a bipolar transistor The similarity in form between (1.21 1 ) and (1.209) is striking. In both cases, the intrinsic device fT increases as the inverse square of the critical device dimension across which carriers are in transit. The voltage VT = 26 mV is fixed for a bipolar transistor, but the fT of an MOS transistor can be increased by operating at high values of (VGS - V r ) Note that the base width WB in a bipolar transistor is a vertical dimension determined by dif- fusion~ or implants and can typically be made much smaller than the channel length L of an MOS transistor, which depends on surface geometry and photolithographic processes. Thus bipolar transistors generally have higher fT than MOS transistors made with compa- rable processing. Finally, (1.209) was derived assuming that the MOS transistor exhibits square-law behavior as in (1.157). However, as described in Section 1.7, submicron MOS transistors depart significantly from square-law characteristics, and we find that for such devices fT is proportional to L-l rather than L - ~ . I EXAMPLE Derive the complete small-signal model for an NMOS transistor with ID = 100 pA, VsB = 1 V, VDS = 2 V. Device parameters are c $ ~ = 0.3 V, W = 10 pm, L = 1 pm, y = 0.5 v " ~ , kt = 200 p m 2 , A = 0.02 V-', to, = 100 angstroms, $0 = 0.6 V, CsbO = CdbO = 10 fF. Overlap capacitance from gate to source and gate to drain is 1 fF. Assume Cgb = 5 fF. From (1.166), Since VDs > V,,, the transistor operates in the saturation or active region. From (1.180), From (1.199), From (1.194), 1 - T O = - - looo kdl = 500 kdl AID 0.02 X 100 Using (1.201) with Vss = 1 V , we find The voltage from drain to body is 60 Chapter 1 Models for Integrated-Circuit Active Devices where %, = 1.5 X 106 Vlm and pn = 0.07 m2/v-s is the low-field mobility close to the gate. Equation 1.212 is also plotted in Fig. 1.39. From (1.212), as % -. W, vd -+ v , , ~ = p,%,. At the critical field value %, the carrier velocity is a factor of 2 less than the low- field formula would predict. In a device with a channel length L = 0.5 pm, we need a voltage drop of only 0.75 V along the channel to produce an average field equal to %, and this condition is readily achieved in short-channel MOS transistors. Similar results are found for PMOS devices. Substituting (1.212) and (1.149) into (1.147) and rearranging gives Note that as %, + W and velocity saturation becomes negligible, (1.213) approaches the original equation (1.147). Integrating (1.21 3) along the channel, we obtain and thus In the limit as 8, --+ a, (1.215) is the same as (1.152), which gives the drain current in the triode region without velocity saturation. The quantity VDs/L in (1.215) can be interpreted as the average horizontal electric field in the channel. If this field is comparable to %, the drain current for a given VDs is less than the simple expression (1.152) would predict. Equation 1.215 is valid in the triode region. Let VDqaCt) represent the maximum value of VDs for which the transistor operates in the triode region, which is equivalent to the minimum value of VDs for which the transistor operates in the active region. In the active region, the current should be independent of VDs because channel-length modulation is not included here. Therefore, VDs(act) is the value of VDs that sets dIDldVDs = 0. From (1.215), where k' = pnCox as given by (1.153). To set dIDldVDs = 0, Rearranging (1.217) gives Solving the quadratic equation gives 1 1.7 Short-Channel Effects in MOS Transistors 61 Since the drain-source voltage must be greater than zero, To determine VDs(act) without velocity-saturation effects, let %, + m so that the drift velocity is proportional to the electric field, and let X = (VGS - Vt)l(%,L). Then X + 0, and a Taylor series can be used to show that Using (1.221) in (1.220) gives When %, + m, (1.222) shows that VDs(actj + (VGS - V/), as expected.28 This observa- tion is confirmed by plotting the ratio of VDscXg to the overdrive V,, versus %,L in Fig. 1.40. When %, + a, VDS(act) + Vov = VGS - Vt, as predicted by (1.222). On the other hand, when %, is small enough that velocity saturation is significant, Fig. 1.40 shows that VDS(act) < Vov. To find the drain current in the active region with velocity saturation, substitute VDS(act) in (1.220) for VDs in (1.215). After rearranging, the result is Equation 1.223 is in the same form as (1.157), where velocity saturation is neglected, except that VDs(act) is less than (VGS - Vt) when velocity saturation is significant, as shown in Fig. 1.40. Therefore, the current predicted by (1.157) overestimates the current that really flows when the carrier velocity saturates. To examine the limiting case when the velocity is completely saturated, let 8, + 0. Then (1.212) shows that the drift velocity approaches the scattering-limited velocity vd --+ v,,l = pn%,. Substituting (1.220) into (1.223) gives Figure 1.40 Ratio of the min- imum drain-source voltage re- quired for operation in the active region to the overdrive versus the product of the critical field and the channel length. When 8, + m, velocity saturation is not a factor, and VnS(act) -+ V,, = VGS - V,, as expected. When velocity saturation is sig- nificant, Vosc,,,, < V,],,. 62 Chapter 1 Models for Integrated-Circuit Active Devices In contrast to the square-law behavior predicted by (1.157), (1.224) shows that the drain current is a linear function of the overdrive (VGS - V t ) when the carrier velocity saturates. Also, (1.224) shows that the drain current is independent of the channel length when the carrier velocity saturates. In this case, both the charge in the channel and the time required for the charge to cross the channel are proportional to L. Since the current is the ratio of the charge in the channel to the time required to cross the channel, the current does not depend on L as long as the channel length is short enough to produce an electric field that is high enough for velocity saturation to occur.29 In contrast, when the carrier velocity is proportional to the electric field instead of being saturated, the time required for channel charge to cross the channel is proportional to because increasing L both reduces the carrier velocity and increases the distance between the source and the drain. Therefore, when velocity saturation is not significant, the drain current is inversely proportional to L, as we have come to expect through (1.157). Finally, (1.224) shows that the drain current in the active region is proportional to the scattering-limited velocity v,,l = p,,%, when the velocity is saturated. Substituting ( l .222) into (1.223) gives where X = (VGS - Vt)/(%, L) as defined for (1.22 1). If X << 1 , (1 - X ) - 141 + X) , and Equation 1.226 is valid without velocity saturation and at its onset, where (VGS - V t ) << %,L. The effect of velocity saturation on the current in the active region predicted by (1.226) can be modeled with the addition of a resistance in series with the source of an ideal square-law device, as shown in Fig. 1.41. Let V& be the gate-source voltage of the ideal square-law transistor. From (1.157), Let VGs be the sum of V& and the voltage drop on R s x Then This sum models the gate-source voltage of a real MOS transistor with velocity saturation. Substituting ( l .228) into (1.227) gives 1.8 Weak lnversion in MOS Transistors 65 Figure 1.42 Transconductance- to-current ratio versus over- drive (VGS - V t ) where velocity saturation is insignif- icant (%, L - m), dominant (%,L = O ) , and of gradu- 3 ally increasing importance (%,L = 0.75 V ) . is inversely proportional to the channel length when the velocity is saturated. In contrast, (1.209) predicts that fT is inversely proportional to the square of the channel length before the velocity saturates. As a result, velocity saturation reduces the speed improvement that can be achieved through reductions in the minimum channel length. 1.7.3 Mobility Degradation from the Vertical Field Thus far, we have considered only the effects of the horizontal field due to the VDs along the channel when considering velocity saturation. However, a vertical field originating from the gate voltage also exists and influences carrier velocity. A physical reason for this effect is that increasing the vertical electric field forces the carriers in the channel closer to the surface of the silicon, where surface imperfections impede their movement from the source to the drain, reducing mobility.31 The vertical field at any point in the channel depends on the gate-channel voltage. Since the gate-channel voltage is not constant from the source to the drain, the effect of the vertical field on mobility should be included within the integration in (1.214) in principle.32 For simplicity, however, this effect is often mod- eled after integration by changing the mobility in the previous equations to an effective mobility given by where p, is the mobility with zero vertical field, and 6 is inversely proportional to the oxide thickness. For to, = 100 A , 6 is typically in the range from 0.1 V-' to 0.4 V-' .33 In practice, 0 is determined by a best fit to measured device characteristics. 1.8 Weak lnversion in MOS Transistors The MOSFET analysis of Section 1.5 considered the normal region of operation for which a well-defined conducting channel exists under the gate. In this region of strong inversion, changes in the gate-source voltage are assumed to cause only changes in the channel charge and not in the depletion-region charge. In contrast, for gate-source voltages less than the extrapolated threshold voltage Vt but high enough to create a depletion region at the surface of the silicon, the device operates in weak inversion. In the weak-inversion region, the 66 Chapter 1 Models for Integrated-Circuit Active Devices channel charge is much less than the charge in the depletion region, and the drain current arising from the drift of majority carriers is negligible. However, the total drain current in weak inversion is larger than that caused by drift because a gradient in minority-carrier concentration causes a diffusion current to flow. In weak inversion, an n-channel MOS transistor operates as an npn bipolar transistor, where the source acts as the emitter, the substrate as the base, and the drain as the collector.34 1.8.1 Drain Current in Weak Inversion To analyze this situation, assume that the source and the body are both grounded. Also assume that VDs > 0. (If VDs < 0, the drain acts as the emitter and the source as the c~ l l ec to r . )~~ Then increasing the gate-source voltage increases the surface potential +, which tends to reduce the reverse bias across the source-substrate (emitter-base) junction and to exponentially increase the concentration of electrons in the p-type substrate at the source np(0). From (1.27), +S np(0) = np, exp - VT where n,, is the equilibrium concentration of electrons in the substrate (base). Similarly, the concentration of electrons in the substrate at the drain np(L) is From (1.3 l), the drain current due to the diffusion of electrons in the substrate is where D, is the diffusion constant for electrons, and A is the cross-sectional area in which the diffusion current flows. The area A is the product of the transistor width W and the thickness X of the region in which ID flows. Substituting (1.243) and (1.244) into (1.245) and rearranging gives W ID = - qXD,np, exp L In weak inversion, the surface potential is approximately a linear function of the gate- source voltage.36 Assume that the charge stored at the oxide-silicon interface is indepen- dent of the surface potential. Then, in weak inversion, changes in the surface potential A+, are controlled by changes in the gate-source voltage AVGs through a voltage divider between the oxide capacitance C,, and the depletion-region capacitance Cj,. Therefore, in which n = (1 + Cj,ICo,) and X = Cj,ICo,, as defined in (1.197). Separating variables in (1.247) and integrating gives where kl is a constant. Equation 1.248 is valid only when the transistor operates in weak inversion. When VGS = Vt with VSB = 0, = 24f by definition of the threshold volt- age. For VGS > Vt, the inversion layer holds the surface potential nearly constant and 1.8 Weak Inversion in MOS Transistors 67 (1.248) is not valid. Since (1.248) is valid only when VGS 5 Vt , (1.248) is rewritten as follows: where k2 = kl + Vtln. Substituting (1 .249) into (1.246) gives W ID = -qXDnnpo exp - exp V ~ s v, 1 -exp -- L ( ) ( v )[ ( ?)l Let It = qXDnnp0 exp - (: ) represent the drain current with VGS = Vt, W / L = 1, and VDs >> VT. Then Figure 1.43 plots the drain current versus the drain-source voltage for three values of the overdrive, with W = 20 pm, L = 20 pm, n .= 1.5, and It = 0.1 pA. Notice that the drain current is almost constant when VDs > 3VT because the last term in (1.252) approaches unity in this case. Therefore, unlike in strong inversion, the minimum drain- source voltage required to force the transistor to operate as a current source in weak in- version is independent of the overdrive.37 Figure 1.43 and Equation 1.252 also show that the drain current is not zero when VGS 5 Vt. TO further illustrate this point, we show measured NMOS characteristics plotted on two different scales in Fig. 1.44. In Fig. 1.44a, we show 6 versus VGS in the active region plotted on linear scales. For this device, W = 20 pm, L = 20 pm, and short-channel effects are negligible. (See Problem 1.21 for an example of a case in which short-channel effects are important.) The resulting straight line shows that the device characteristic is close to an ideal square law. Plots like the one in Fig. 1 . 4 4 ~ are commonly used to obtain Vt by extrapolation (0.7 V in this case) and also k' from the slope of the curve (54 p N v 2 in this case). Near the threshold voltage, the curve deviates from the straight line representing the square law. This region is weak inversion. The data are plotted a second time in Fig. 1.44b on log-linear scales. The straight line obtained for VGS < Vt fits (1.252) with n = 1.5. For ID < 10-l2 A, the slope decreases because leakage currents are significant and do not follow (1.252). Figure 1.43 Drain cur- rent versus drain-source voltage in weak inversion. Chapter 1 Models for Integrated-Circuit Active Devices the remainder of this book and assume that MOS transistors operate in weak inversion for overdrives less than the bound given in (1.255). Equation 1.208 can be used to find the transition frequency. In weak inversion, C,, = Cgd = 0 because the inversion layer contains little charge.39 However, Cgb can be thought of as the series combination of the oxide and depletion capacitors. Therefore, Substituting (1.253) and (1.256) into (1.208) gives Let IM represent the maximum drain current that flows in the transistor in weak inversion. Then where I , is given in (1.251). Multiplying numerator and denominator in (1.257) by IM and using (1.258) gives From (1.251), It D,. Using the Einstein relationship D, = p,Vr gives Equation 1.260 shows that the transition frequency for an MOS transistor operating in weak inversion is inversely proportional to the square of the channel length. This result is consistent with (1.209) for strong inversion without velocity saturation. In contrast, when velocity saturation is significant, the transition frequency is inversely proportional to the channel length, as predicted by (1.241). Equation 1.260 also shows that the transition fre- quency in weak inversion is independent of the overdrive, unlike the case in strong inver- sion without velocity saturation, but like the case with velocity saturation. Finally, a more detailed analysis shows that the constant of proportionality in (1.260) is approximately unity.39 EXAMPLE Calculate the overdrive and the transition frequency for an NMOS transistor with ID = 1 pA, It = 0.1 pA, and VDs >> Vr . Device parameters are W = 10 pm, L = 1 pm, n = 1.5, k' = 200 ~ A / v ~ , and to, = 100 A . Assume that the temperature is 27•‹C. From (1.166), if the transistor operates in strong inversion, 1.9 Substrate Current Flow in MOS Transistors 71 Since the value of the overdrive calculated by (1.166) is less than 2nVT -- 78 mV, the overdrive calculated previously is not valid except to indicate that the transistor does not operate in strong inversion. From (1.252), the overdrive in weak inversion with VDs >> VT is V, = nVT ln - - = (1.5)(26 mV) ln (: 4 ) From (1 L?%), From (1.247), Cjs = (n - l)Cox = (0.5)COx From (1.256), cgs + cgb + cgd - Cgb = W L cox(o.~cox) c o x = WL- C,, + 0.5COx 3 From (1.208), 1 26 = 360 MHz fT = GO' = - 271. 11.5fF Although 360 MHz may seem to be a high transition frequency at first glance, this result should be compared with the result of the example at the end of Section 1.6, where the same transistor operating in strong inversion with an overdrive of 3 16 mV had a transition frequency of 3.4 GHz. 1.9 Substrate Current Flow in MOS Transistors In Section 1.3.4, the effects of avalanche breakdown on bipolar transistor characteristics were described. As the reverse-bias voltages on the device are increased, carriers travers- ing the depletion regions gain sufficient energy to create new electron-hole pairs in lattice collisions by a process known as impact ionization. Eventually, at sufficient bias volt- ages, the process results in large avalanche currents. For collector-base bias voltages well below the breakdown value, a small enhanced current flow may occur across the collector- base junction due to this process, with little apparent effect on the device characteristics. Impact ionization also occurs in MOS transistors but has a significantly different effect on the device characteristics. This difference is because the channel electrons (for the NMOS case) create electron-hole pairs in lattice collisions in the drain depletion region, and some of the resulting holes then flow to the substrate, creating a substrate current. (The electrons created in the process flow out the drain terminal.) The carriers created by impact ionization are therefore not confined within the device as in a bipolar transistor. The effect of this phenomenon can be modeled by inclusion of a controlled current generator 72 Chapter 1 Models for Integrated-Circuit Active Devices Figure 1.46 Representation of impact ionization in an MOSFET by a drain-substrate current generator. IDB from drain to substrate, as shown in Fig. 1.46 for an NMOS device. The magnitude of this substrate current depends on the voltage across the drain depletion region (which determines the energy of the ionizing channel electrons) and also on the drain current (which is the rate at which the channel electrons enter the depletion region). Empirical investigation has shown that the current IDB can be expressed as where K I and K2 are process-dependent parameters and VDs(act) is the minimum value of VDs for which the transistor operates in the active region.40 Typical values for NMOS devices are K1 = 5 V-l and KZ = 30 V. The effect is generally much less significant in PMOS devices because the holes carrying the charge in the channel are much less efficient in creating electron-hole pairs than energetic electrons. The major impact of this phenomenon on circuit performance is that it creates a par- asitic resistance from drain to substrate. Because the common substrate terminal must always be connected to the most negative supply voltage in the circuit, the substrate of an NMOS device in a p-substrate process is an ac ground. Therefore, the parasitic resis- tance shunts the drain to ac ground and can be a limiting factor in many circuit designs. Differentiating (1.261), we find that the drain-substrate small-signal conductance is where the gate and the source are assumed to be held at fixed potentials. EXAMPLE Calculate rdb = l / g d b for VDS = 2 V and 4 V, and compare with the device r,. Assume ID = 100 pA, A = 0.05 V-', VDs(act) = 0.3 V, K1 = 5 V-', and KZ = 30 V. For VDs = 2 V, we have from (1.261) IDB = 5 X 1.7 X 100 X 1 0 - ~ X exp - - = 1.8 X 10-l1 A ( :.;) From (1.262), and thus Problems 75 (continued) Quantity Formula Small-Signal Operation (Active Region) Drain-body depletion capacitance Cdb = C d b0 (l + 2)"' Gate-source capacitance 2 c,, = -WLC,, 3 Transition frequency PROBLEMS l . l (a) Calculate the built-in potential, depletion-layer depths, and maximum field in a plane-abrupt pn junction in silicon with dop- ing densities NA = 8 X l O I 5 atoms/cm3 and No = 1017 atoms/cm3. Assume a reverse bias of S V. (b) Repeat (a) for zero external bias and 0.3 V fonvard bias. 1.2 Calculate the zero-bias junction capaci- tance for the example in Problem 1.1, and also cal- culate the value at 5 V reverse bias and 0.3 V for- ward bias. Assume a junction area of 2 X 10-5 cm2. 1.3 Calculate the breakdown voltage for the junction of Problem 1 . l if the critical field is = 4 X 105 V/cm. 1.4 If junction curvature causes the maximum field at a practical junction to be 1 .S times the theo- retical value, calculate the doping density required to give a breakdown voltage of 150 V with an abrupt pn junction in silicon. Assume that one side of the junction is much more heavily doped than the other and = 3 X 105 V/cm. 1.5 If the collector doping density in a transistor is 6 X 1015 atoms/cm3, and is much less than the base doping, find BVcEo for pF = 200 and n = 4. Use %," = 3 X 105 V/cm. 1.6 Repeat Problem 1 .S for a doping density of 10i5 atoms/cm3 and pF = 400. 1.7(a) Sketch the Ic-VcE characteristics in the forward-active region for an npn transistor with PF = 100 (measured at low V C ~ ) , V A = 50 V, BVc~o = 120 V, and n = 4. Use where M is given by (1.78). Plot Zc from 0 to 10 mA and VCE from 0 to 50 V. Use IB = 1 pA, 10 FA, 30 FA, and 60 FA. (b) Repeat (a), but sketch VCE from 0 to 10 V. 1.8 Derive and sketch the complete small- signal equivalent circuit for a bipolar transistor at Ic = 0.2 mA, VcB = 3 V, Vcs = 4 V. De- vice parameters are Cjeo = 20 fF, CPo = 10 fF, ccs0 = 2 0 ~ p 0 = 1 0 0 , ~ ~ = i5Ps ,q = 1 0 - ~ , rb = 200 a , r, = 100 0 , r,, = 4 R, and r, = 5por,. Assume I,!Q = 0.55 V for all junc- tions. 1.9 Repeat Problem 1.8 for Ic = 1 mA, V- = l V , a n d Vcs = 2V. 1.10 Sketch the graph of small-signal, common-emitter current gain versus frequency on log scales from 0.1 MHz to 1000 MHz for the examples of Problems 1.8 and 1.9. Calculate the fT of the device in each case. 1.1 1 An integrated-circuit npn transistor has the following measured characteristics: rb = loo a , r, = loo a, p, = loo, r, = 50 k a at Ic = 1 mA, fT = 600 MHz with Ic = 1 mA and VCB = 10 V, fT = 1 GHz with Ic = 10 mA and VcB = 10 V, C, = 0.15 pF with VCB = 10 V, and C,, = 1 pF with Vcs = 10 V. Assume $0 = 0.55 V for all junctions, and assume C,, is constant in the forward-bias region. Use r, = 5poro. (a) Form the complete small-signal equivalent circuit for this transistor at Ic = 0.1 mA, 1 mA, and 5 mA with VcB = 2 V and Vcs = 15 V. (b) Sketch the graph of fT versus Ic for this transistor on log scales from 1 pA to 10 mA with VCB = 2 V. 1 76 Chapter 1 Models for Integrated-Circuit Active Devices 1.12 A lateral pnp transistor has an effective base width of 10 pm ( l pm = 10-4 cm). (a) If the emitter-base depletion capacitance is 2 pF in the forward-bias region and is constant, cal- culate the device fT at Ic = -0.5 mA. (Neglect C,.) Also, calculate the minority-carrier charge stored in the base of the transistor at this current level. Data : Dp = 13 cm2/s in silicon. (b) If the collector-base depletion layer width changes 0.11 p m per volt of V C E , calculate r, for this transistor at Ic = -0.5 mA. 1.13 If the area of the transistor in Problem 1.11 is effectively doubled by connecting two transistors in parallel, which model parameters in the small- signal equivalent circuit of the composite transistor would differ from those of the original device if the total collector current is unchanged? What is the relationship between the parameters of the compos- ite and original devices? 1.14 An integrated npn transistor has the fol- lowing characteristics: r~ = 0.25 ns, small-signal, short-circuit current gain is 9 with Ic = 1 mA at f = 50 MHz, V A = 40 V, PO = 100, rh = 150R, r , = 150R, C, = 0.6pF,C,, = 2 p F a t the bias voltage used. Determine all elements in the small-signal equivalent circuit at Ic = 2 mA and sketch the circuit. 1.15 An NMOS transistor has parameters W = 10 pm, L = 1 pm, k' = 194 pNV2, A = 0.024 V-', to, = 80A, c$f = 0.3 V, Vro = 0.6 V, and N A = 5 X 10IS atoms/cm3. Ignore velocity saturation effects. (a) Sketch the ID-VDS characteristics for VDs from 0 to 3 V and Vcs = 0.5 V, 1 .S V, and 3 V. Assume VsB = 0. (b) Sketch the ID-VGs characteristics for VDs = 2 V as VGS varies from 0 to 2 V with VSB = 0,0.5 V, and 1 V. 1.16 Derive and sketch the complete small- signal equivalent circuit for the device of Problem 1.15 with VGS = 1 V, VDS = 2V,and VSB = 1 V. Use $0 = 0.7 V, CsbO = CdbO = 20 fF, and Cgb = 5 fF. Overlap capacitance from gate to source and gate to drain is 2 fF. REFERENCES 1. P. E. Gray, D. DeWitt, A. R. Boothroyd, J. F. Gibbons. Physical Electronics and Circuit Models of Transistors. Wiley, New York, 1964, p. 20. 1.17 Use the device data of Problems 1.15 and 1.16 to calculate the frequency of unity current gain of this transistor with VDs = 3 V, Vss = 0 V, VGS = 1 V, 1.5 V, and 2 V. 1.18 Examine the effect of velocity saturation on MOSFET characteristics by plotting ID - VDs curves for Vcs = 1 V, 2 V, and 3 V, and VDs = 0 to 3 V in the following cases, and by comparing the results with and without inclusion of velocity saturation effects. Assume Vss = 0, Vto = 0.6 V, k' = 194 A = 0, and'&, = 1.5 X 106 Vlm. (a) W = 100 pm and L = 10 pm. (b) W = 10 pm and L = 1 pm. (C) W = 5 p m a n d L = 0.5pm. 1.19 Consider an NMOS transistor with W = 2 pm, L = 0.5 pm, k' = 194 pA/V2, A = 0, Vro = 0.6 V, and 8, = 1.5 X 106 Vlm. Compare the drain current predicted by the model of Fig. 1.41 to the drain current predicted by direct calcu- lation using the equations including velocity satu- ration for VGS from 0 to 3 V. Assume VDs = 3 V and VsB = 0. For what range of VGS is the model of Fig. 1.41 accurate within 10 percent? 1.20 Calculate the transconductance of an n-channel MOSFET with W = 10 pm, p, = 450 cm2/(v-S), and 8, = 1.5 X 106 V/m using channel lengths from 10 p m to 0.4 pm. Assume that t , , = L150 and that the device operates in the active region with VGS - Vt = 0.1 V. Compare the result to a calculation that ignores velocity sat- uration. For what range of channel lengths is the model without velocity saturation accurate within 10 percent? 1.21 Plot & versus VGS for an n-channel MOSFET with W = 1 pm, L = 1 pm, k' = 54 p m 2 , h = 0, VDS = 5 V, VSB = 0, Vto = 0.7 V, and 8, = 1.5 X 106 Vlm. Ignore subthresh- old conduction. Compare the plot with Fig. 1.441 and explain the main difference for large VGS. 1.22 Calculate the transconductance of an n- channel MOSFET at ID = 10 nA and V D ~ = 1 V, assuming subthreshold operation and n = 1.5. As- suming (C,, + CKd + Cgb) = 10 fF, calculate the corresponding device fT . 2. H. C. Poon and H. K. Gummel. "Modeling of Emitter Capacitance," Proc. IEEE, Vol. 57, pp. 218 1-2182, December 1969. 3. B. R. Chawla and H. K. Gummel. "Tran- sition Region Capacitance of Diffused pn Junc- tions," IEEE Trans. Electron Devices, Vol. ED-18, pp. 178-195, March 1971. 4. S. L. Miller. "Avalanche Breakdown in Germanium," Phys. Rev., Vol. 99, p. 1234, 1955. 5. A. S. Grove. Physics and Technology of Semiconductor Devices. Wiley, New York, 1967, Ch. 6. 6. A. S. Grove. Op. cit., Ch. 4. 7. A. S. Grove. Op. cit., Ch. 7. 8. P. E. Gray et al. Op. cit., p. 10. 9. P. E. Gray et al. Op. cit., p. 129. 10. P. E. Gray et al. Op. cit., p. 180. 11. B. A. McDonald. "Avalanche Degradation of hFE," IEEE Trans. Electron Devices, Vol. ED- 17, pp. 871-878, October 1970. 12. H. DeMan. "The Influence of Heavy Dop- ing on the Emitter Efficiency of a Bipolar Transis- tor," IEEE Trans. Electron Devices, Vol. ED-18, pp. 833-835, October 197 1. 13. R. J. Whittier and D. A. Tremere. "Current Gain and Cutoff Frequency Falloff at High Cur- rents," IEEE Trans. Electron Devices, Vol. ED-16, pp. 39-57, January 1969. 14. J. L. Moll and I. M. Ross. "The Dependence of Transistor Parameters on the Distribution of Base Layer Resistivity," Proc. IRE, Vol. 44, p. 72, 1956. 15. P. E. Gray et al. Op. cit., Ch. 8. 16. R. S. Muller andT. I. Kamins. Device Elec- tronics for Integrated Circuits. Second Edition, Wi- ley, New York, 1986, p. 386. 17. Y. P. Tsividis. Operation and Modeling of the MOS Transistor. McGraw-Hill, New York, 1987, p. 141. 18. D. Frohman-Bentchkowsky and A. S. Grove. "Conductance of MOS Transistors in Satu- GENERAL REFERENCES I. Getreu. Modelling the Bipolar Transistor. Tektronix Inc., 1976. P. E. Gray and C. L. Searle, Electronic Princi- ples. Wiley, New York, 1969. General References 77 ration," IEEE Trans. Electron Devices, Vol. ED- 16, pp. 108-113, January 1969. 19. S. M. Sze. Physics of Semiconductor De- vices. Second Edition, Wiley, New York, 1981, pp. 451-452. 20. R. S. Muller and T. I. Kamins. Op. cit., p. 17. 21. Y. P. Tsividis. Op. cit., p. 148. 22. R. S. Muller and T. I. Kamins. Op. cit., pp. 490496. 23. Y. P. Tsividis. Op. cit., pp. 150-151 and 198-200. 24. R. S. Muller and T. I. Kamins. Op. cit., p. 496. 25. ' Y. P. Tsividis. Op. cit., p. 151. 26. Y. P. Tsividis. Op. cit., pp. 310-328. 27. R. S. Muller and T. I. Kamins. Op. cit., p. 480. 28. R. S. Muller and T. I. Kamins. Op. cit., p. 482. 29. Y. P. Tsividis. Op. cit., p. 181. 30. Y. P. Tsividis. Op. cit., p. 294. 31. Y. P. Tsividis. Op. cit., p. 142. 32. R. S. Muller and T. I. Kamins. Op. cit., p. 484. 33. Y. P. Tsividis. Op. cit., p. 146. 34. S. M. Sze. Op. cit., p. 446. 35. Y. P. Tsividis. Op. cit., p. 136. 36. Y. P. Tsividis. Op. cit., p. 83. 37. Y. P. Tsividis. Op. cit., p. 139. 38. Y. P. Tsividis. Op. cit., p. 137. 39. Y. P. Tsividis. Op. cit., p. 324. 40. K. Y. Toh, P. K. KO, and R. G. Meyer. "An Engineering Model for Short-Channel MOS De- vices," IEEE Journal of Solid-State Circuits, Vol. 23, pp. 950-958, August 1988. R. S. Muller and T. I Kamins. Device Electron- ics for Integrated Circuits. Wiley, New York, 1986. Y. P. Tsividis. Operation and Modeling of the MOS Transistor. McGraw-Hill, New York, 1987. 80 Chapter 2 Bipolar, MOS, a n d BiCMOS Integrated-Circuit Technology 10 Figure 2.1 Hole and electron 1014 lo i5 1oi6 10" 1 0 ' ~ 10'' 10" 10" mobility as a function of Total impurity concentration (cm3) doping in silicon3 is an increase in the ohmic conductivity of the material itself. This conductivity is given by where pn (cm2N-S) is the electron mobility, p p (cm2/V-S) is the hole mobility, and a (0-cm)-' is the electrical conductivity. For an n-type sample, substitution of (2.1) and (2.6) in (2.7) gives For a p-type sample, substitution of (2.2) and (2.6) in (2.7) gives The mobility p is different for holes and electrons and is also a function of the impurity concentration in the crystal for high impurity concentrations. Measured values of mobility in silicon as a function of impurity concentration are shown in Fig. 2.1. The resistivity p (&cm) is usually specified in preference to the conductivity, and the resistivity of n- and p-type silicon as a function of impurity concentration is shown in Fig. 2.2. The conductivity and resistivity are related by the simple expression p = l l a . 2.2.2 Solid-state Diffusion Solid-state diffusion of impurities in silicon is the movement, usually at high temperature, of impurity atoms from the surface of the silicon sample into the bulk material. During this high-temperature process, the impurity atoms replace silicon atoms in the lattice and are termed substitutional impurities. Since the doped silicon behaves electrically as p-type or n-type material depending on the type of impurity present, regions of p-type and n-type material can be formed by solid-state diffusion. The nature of the diffusion process is illustrated by the conceptual example shown in Figs. 2.3 and 2.4. We assume that the silicon sample initially contains a uniform con- centration of n-type impurity of 1015 atoms per cubic centimeter. Commonly used n-type impurities in silicon are phosphorus, arsenic, and antimony. We further assume that by 2.2 Basic Processes in Integrated-Circuit Fabrication 81 0.0001 1014 10'5 1016 10" 1018 loi9 1oZ0 Impurity concentration (cm") Figure 2.2 Resistivity of p- and n-type silicon as a function of impurity c~ncentration.~ 1 ly n-type sample Boron Impurity concentration, atoms/cm3 Figure 2.3 An n-type silicon sample with boron (pm) deposited on the surface. some means we deposit atoms of p-type impurity on the top surface of the silicon sam- ple. The most commonly used p-type impurity in silicon device fabrication is boron. The distribution of impurities prior to the diffusion step is illustrated in Fig. 2.3. The initial placement of the impurity atoms on the surface of the silicon is called the predeposition step and can be accomplished by a number of different techniques. If the sample is now subjected to a high temperature of about 1100•‹C for a time of about one hour, the impurities diffuse into the sample, as illustrated in Fig. 2.4. Within the silicon, the regions in which thep-type impurities outnumber the original n-type impurities display p-type electrical behavior, whereas the regions in which the n-type impurities are 82 Chapter 2 Bipolar, MOS, a n d BiCMOS Integrated-Circuit Technology Boron atoms diffuse --X lnto the sample F n-type sample I Impurity concentration, atoms/cm3 1 oi8 1oi7 , Figure 2.4 Distribution of impurities after Depth, (V) diffusion. more numerous display n-type electrical behavior. The diffusion process has allowed the formation of a pn junction within the continuous crystal of silicon material. The depth of this junction from the surface varies from 0.1 p m to 20 p m for silicon integrated-circuit diffusions (where 1 p m = 1 micrometer = 1W6 m). 2.2.3 Electrical Properties of Diffused Layers The result of the diffusion process is often a thin layer near the surface of the silicon sample that has been converted from one impurity type to another. Silicon devices and integrated circuits are constructed primarily from these layers. From an electrical standpoint, if the pn junction formed by this diffusion is reverse biased, then the layer is electrically isolated from the underlying material by the reverse-biased junction, and the electrical properties of the layer itself can be measured. The electrical parameter most often used to characterize such layers is the sheet resistance. To define this quantity, consider the resistance of a uni- formly doped sample of length L, width W, thickness T, and n-type doping concentration No, as shown in Fig. 2.5. The resistance is Figure 2.5 Rectangular sample for calculation of sheet resistance.