i2C BUS speficication / philips 2000

i2C BUS speficication / philips 2000

(Parte 1 de 17)

THE I 2C-BUS SPECIFICATION

Philips Semiconductors The I2C-bus specification

1PREFACE3
1.1Version 1.0 - 19923
1.2Version 2.0 - 1983
1.3Version 2.1 - 19993
1.4Purchase of Philips I2C-bus components3
AND MANUFACTURERS4
2.1Designer benefits4
2.2Manufacturer benefits6

2THE I2C-BUS BENEFITS DESIGNERS

SPECIFICATION6
4THE I2C-BUS CONCEPT6
5GENERAL CHARACTERISTICS8
6BIT TRANSFER8
6.1Data validity8
6.2START and STOP conditions9
7TRANSFERRING DATA10
7.1Byte format10
7.2Acknowledge10

3INTRODUCTION TO THE I2C-BUS

GENERATION1
8.1Synchronization1
8.2Arbitration12
mechanism as a handshake13
9FORMATS WITH 7-BIT ADDRESSES13
107-BIT ADDRESSING15
10.1Definition of bits in the first byte15
10.1.1General call address16
10.1.2START byte17
10.1.3CBUS compatibility18

8ARBITRATION AND CLOCK 8.3Use of the clock synchronizing

MODE I2C-BUS SPECIFICATION19
12FAST-MODE19
13Hs-MODE20
13.1High speed transfer20
13.2Serial data transfer format in Hs-mode21
back23
13.4Hs-mode devices at lower speed modes24
system24
system25
system25
mixed-speed bus system27
1410-BIT ADDRESSING27
14.1Definition of bits in the first two bytes27
14.2Formats with 10-bit addresses27
10-bit addressing30

11EXTENSIONS TO THE STANDARD- 13.3Switching from F/S- to Hs-mode and 13.5Mixed speed modes on one serial bus 13.5.1F/S-mode transfer in a mixed-speed bus 13.5.2Hs-mode transfer in a mixed-speed bus 13.5.3Timing requirements for the bridge in a 14.3General call address and start byte with

AND BUS LINES30
15.1Standard- and Fast-mode devices30
15.2Hs-mode devices34

15ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES

16ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THE BUS LINES . 37

16.1Maximum and minimum values of

I2C-bus devices39
17APPLICATION INFORMATION41

resistors Rp and Rs for Standard-mode

Fast-mode I2C-bus devices41
I2C-bus devices41
17.3Wiring pattern of the bus lines42

17.1Slope-controlled output stages of 17.2Switched pull-up circuit for Fast-mode 17.4Maximum and minimum values of

I2C-bus devices42

resistors Rp and Rs for Fast-mode 17.5Maximum and minimum values of

I2C-bus devices42

resistors Rp and Rs for Hs-mode

FOR F/S-MODE I2C-BUS SYSTEMS42

18BI-DIRECTIONAL LEVEL SHIFTER

logic levels43
18.1.1Operation of the level shifter4

18.1Connecting devices with different

FROM PHILIPS45

19DEVELOPMENT TOOLS AVAILABLE 20SUPPORT LITERATURE . . . . . . . . . . . . . 46

Philips Semiconductors The I2C-bus specification

This version of the 1992 I2C-bus specification includes the following modifications:

•Programming of a slave address by software has been omitted. The realization of this feature is rather complicated and has not been used.

•The “low-speed mode” has been omitted. This mode is, in fact, a subset of the total I2C-bus specification and need not be specified explicitly.

•The Fast-mode is added. This allows a fourfold increase of the bit rate up to 400kbit/s. Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100kbit/s I2C-bus system.

•10-bit addressing is added. This allows 1024 additional slave addresses.

•Slope control and input filtering for Fast-mode devices is specified to improve the EMC behaviour.

NOTE: Neither the 100kbit/s I2C-bus system nor the 100kbit/s devices have been changed.

The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher bus speeds and lower supply voltages. This updated version of the I2C-bus specification meets those requirements and includes the following modifications:

•The High-speed mode (Hs-mode) is added. This allows an increase in the bit rate up to 3.4Mbit/s. Hs-mode devices can be mixed with Fast- and Standard-mode devices on the one I2C-bus system with bit rates from 0 to 3.4Mbit/s.

•The low output level and hysteresis of devices with a supply voltage of 2V and below has been adapted to meet the required noise margins and to remain compatible with higher supply voltage devices.

•The 0.6V at 6mA requirement for the output stages of Fast-mode devices has been omitted.

•The fixed input levels for new devices are replaced by bus voltage-related levels.

•Application information for bi-directional level shifter is added.

1.3Version 2.1 - 2000

Version 2.1 of the I2C-bus specification includes the following minor modifications:

•After a repeated START condition in Hs-mode, it is possible to stretch the clock signal SCLH (see Section13.2 and Figs22, 25 and 32).

•Some timing parameters in Hs-mode have been relaxed (see Tables6 and 7).

1.4Purchase of Philips I2C-bus components

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips.

Philips Semiconductors The I2C-bus specification

2THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS

In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes:

•Some intelligent control, usually a single-chip microcontroller

•General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data converters

•Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, or DTMF generators for telephones with tone dialling.

To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. At present, Philips’ IC range includes more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in all three of the previously mentioned categories. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits.

Here are some of the features of the I2C-bus:

•Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)

•Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers

•It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer

•Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100kbit/s in the Standard-mode, up to 400kbit/s in the Fast-mode, or up to 3.4Mbit/s in the High-speed mode

•On-chip filtering rejects spikes on the bus data line to preserve data integrity

•The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF.

(Parte 1 de 17)

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